Semiconductor device and method for measuring current of semiconductor device

ABSTRACT

A semiconductor device in which a transistor has the characteristic of low off-state current is provided. The transistor comprises an oxide semiconductor layer having a channel region whose channel width is smaller than 70 nm. A temporal change in off-state current of the transistor over time can be represented by Formula (a2). In Formula (a2), I OFF  represents the off-state current, t represents time during which the transistor is off, α and τ are constants, β is a constant that satisfies 0&lt;β≤1, and C S  is a constant that represents load capacitance of a source or a drain. 
     
       
         
           
             
               
                 
                   
                     
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BACKGROUND OF THE INVENTION 1. Field of the Invention

One embodiment of the present invention relates to a semiconductordevice and a method for measuring a current of the semiconductor device.

The present invention relates to an object, a method, or a manufacturingmethod. In addition, the present invention relates to a process, amachine, manufacture, or a composition of matter. One embodiment of thepresent invention relates to a display device, a light-emitting device,a power storage device, a memory device, a driving method thereof, or amanufacturing method thereof.

In this specification and the like, a semiconductor device generallymeans a device that can function by utilizing semiconductorcharacteristics. In some cases, a display device, an electro-opticaldevice, a semiconductor circuit, or an electronic device includes asemiconductor device.

2. Description of the Related Art

Attention has been focused on a technique for forming a transistor usinga semiconductor thin film formed over a substrate having an insulatingsurface (also referred to as thin film transistor (TFT)). Suchtransistors are applied to a wide range of electronic devices such as anintegrated circuit (1C) and an image display device (display device). Asemiconductor material typified by silicon is widely known as a materialfor a semiconductor thin film that can be used for a transistor, and anoxide semiconductor has been attracting attention as well.

For example, a technique for manufacturing a transistor using zinc oxideor an In—Ga—Zn oxide semiconductor is disclosed (see Patent Document 1).

In order to manufacture semiconductor devices that need chargeretention, such as liquid crystal display devices, it is very importantto know the characteristics of transistors in an off state (hereinafterreferred to as off-state current), and the like. This is because theparameters of a thin film transistor such as channel length and channelwidth are determined in accordance with the characteristics of thetransistor in an off state.

Patent Document 2 discloses an evaluation method with which currentvalues lower than or equal to 1×10⁻²⁴ A can be measured.

REFERENCE Patent Document

-   [Patent Document 1] Japanese Published Patent Application No.    2007-123861-   [Patent Document 2] Japanese Published Patent Application No.    2011-237418

Non-Patent Document

-   [Non-Patent Document 1] P. Bordewijk, “Defect-diffusion models of    dielectric relaxation,” Chemical Physics Letters, Vol. 32, issue 3,    1975, Elsevier, pp. 592-596.

SUMMARY OF THE INVENTION

An object of one embodiment of the present invention is to provide acurrent measurement method capable of measuring an extremely lowcurrent. Another object of one embodiment of the present invention is toprovide an inspection method of a semiconductor device utilizing thecurrent measurement method. Another object of one embodiment of thepresent invention is to provide a semiconductor device employing thecurrent measurement method. Another object of one embodiment of thepresent invention is to provide a semiconductor device employing theinspection method. Another object of one embodiment of the presentinvention is to provide a characteristic evaluation circuit. Anotherobject of one embodiment of the present invention is to provide a novelmeasurement method. Another object of one embodiment of the presentinvention is to provide a novel semiconductor device.

Note that the descriptions of a plurality of objects do not preclude theexistence of each object. One embodiment of the present invention doesnot necessarily achieve all the objects listed above. Objects other thanthose listed above are apparent from the description of thespecification, drawings, claims, and the like, and such objects can bean object of one embodiment of the present invention.

One embodiment of the present invention is a current measurement methodof a transistor. The current measurement method includes a first step inwhich a charge is written to a first terminal of a capacitor through atransistor under test; a second step in which the transistor under testis turned off to make the first terminal of the capacitor electricallyfloating; a third step in which data on a correspondence between apotential of the first terminal of the capacitor and measuring time isgenerated; a fourth step in which fitting of Formula (a1) to the data isperformed to determine α, β, and τ in Formula (a1), where V_(FN)represents the potential of the first terminal of the capacitor and trepresents the measuring time; and a fifth step in which an off-statecurrent of the transistor under test is calculated by substituting α, β,and τ in Formula (a1) determined in the fourth step into α, β, and τ inFormula (a2), where I_(OFF) represents the off-state current of thetransistor under test, C_(S) represents capacitance of the capacitor,and t represents the measuring time.

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 1} \right\rbrack & \; \\{{V_{FN}(t)} = {\alpha \times e^{- {(\frac{t}{\tau})}^{\beta}}}} & ({a1}) \\\left\lbrack {{Formula}\mspace{14mu} 2} \right\rbrack & \; \\{{I_{OFF}(t)} = {C_{S} \times \frac{\alpha \times \beta}{\tau^{\beta}} \times \tau^{\beta - 1} \times e^{- {(\frac{t}{\tau})}^{\beta}}}} & ({a2})\end{matrix}$

In the above embodiment, a gate of the transistor is electricallyconnected to the first terminal of the capacitor. A current flowingbetween a source and a drain of the transistor is measured to measurethe potential of the first terminal of the capacitor.

In the above embodiment, the measuring time is preferably greater thanor equal to 5×10² seconds and less than or equal to 1×10⁵ seconds.

In the above embodiment, the transistor under test preferably containsan oxide semiconductor in a channel.

One embodiment of the present invention is a transistor whose channelwidth is smaller than 70 nm. A change in off-state current of thetransistor over time can be represented by Formula (a2). In Formula(a2), I_(OFF) represents the off-state current, t represents time duringwhich the transistor is off, α and τ are constants. P is a constant thatsatisfies 0<β≤1, and C_(S) is a constant that represents loadcapacitance of a source or a drain.

In the above embodiment, the off-state current at room temperature isless than 1×10⁻²⁰ A when t is 1×10⁵ seconds.

In the above embodiment, the transistor preferably contains an oxidesemiconductor in a channel.

One embodiment of the present invention is a semiconductor deviceincluding a transistor and a capacitor. A first terminal of thetransistor is electrically connected to a terminal of the capacitor. Achannel width of the transistor is smaller than 70 nm. A change inoff-state current of the transistor over time can be represented byFormula (a2). In Formula (a2), I_(OFF) represents the off-state current,t represents time during which the transistor is off, α and τ areconstants, β is a constant that satisfies 0<β≤1, and C_(S) is a constantthat represents capacitance of the capacitor.

In the above embodiment, the off-state current at room temperature ispreferably less than 1×10⁻²⁰ A when t is 1×10⁵ seconds.

In the above embodiment, the transistor preferably contains an oxidesemiconductor in a channel.

Note that in this specification, ordinal numbers such as “first”,“second”, and “third” are used in order to avoid confusion amongcomponents, and the terms do not limit the components numerically.

Note that in this specification, terms for describing arrangement, suchas “over”, “above”, “under”, and “below”, are used for convenience indescribing a positional relation between components with reference todrawings. The positional relation between components is changed asappropriate in accordance with a direction in which each component isdescribed. Thus, there is no limitation on terms used in thisspecification, and description can be made appropriately depending onthe situation.

In this specification and the like, a transistor is an element having atleast three terminals of a gate, a drain, and a source. The transistorhas a channel region between a drain (a drain terminal, a drain region,or a drain electrode) and a source (a source terminal, a source region,or a source electrode), and current can flow through the drain region,the channel region, and the source region. Note that in thisspecification and the like, a channel region refers to a region throughwhich current mainly flows.

Functions of a source and a drain might be switched when transistorshaving different polarities are employed or a direction of current flowis changed in circuit operation, for example. Thus, the terms “source”and “drain” can be replaced with each other in this specification.

Note that the terms “film” and “layer” can be interchanged with eachother depending on the case or circumstances. For example, the term“conductive layer” can be changed into the term “conductive film” insome cases. In addition, the term “insulating film” can be changed intothe term “insulating layer” in some cases.

For example, in this specification and the like, an explicit description“X and Y are connected” means that X and Y are electrically connected, Xand Y are functionally connected, and X and Y are directly connected.Accordingly, without being limited to a predetermined connectionrelationship, for example, a connection relation relationship shown indrawings or texts, another connection relationship is included in thedrawings or the texts.

Here, each of X and Y denotes an object (e.g., a device, an element, acircuit, a wiring, an electrode, a terminal, a conductive film, or alayer).

Examples of the case where X and Y are directly connected include thecase where an element that enables electrical connection between X and Y(e.g., a switch, a transistor, a capacitor, an inductor, a resistor, adiode, a display element, a light-emitting element, or a load) is notconnected between X and Y, and the case where X and Y are connectedwithout the element that enables electrical connection between X and Yprovided therebetween.

For example, in the case where X and Y are electrically connected, oneor more elements that enable electrical connection between X and Y(e.g., a switch, a transistor, a capacitor, an inductor, a resistor, adiode, a display element, a light-emitting element, or a load) can beconnected between X and Y. Note that the switch is controlled to beturned on or off. That is, the switch is conducting or not conducting(is turned on or off) to determine whether current flows therethrough.Alternatively, the switch has a function of selecting and changing acurrent path. Note that the case where X and Y are electricallyconnected includes the case where X and Y are directly connected.

For example, in the case where X and Y are functionally connected, oneor more circuits that enable functional connection between X and Y(e.g., a logic circuit such as an inverter, a NAND circuit, or a NORcircuit; a signal converter circuit such as a D/A converter circuit, anA/D converter circuit, or a gamma correction circuit; a potential levelconverter circuit such as a power supply circuit (e.g., a step-upcircuit or a step-down circuit) or a level shifter circuit for changingthe potential level of a signal; a voltage source; a current source; aswitching circuit; an amplifier circuit such as a circuit that canincrease signal amplitude, the amount of current, or the like, anoperational amplifier, a differential amplifier circuit, a sourcefollower circuit, or a buffer circuit; a signal generation circuit; astorage circuit; or a control circuit) can be connected between X and Y.Note that for example, in the case where a signal output from X istransmitted to Y even when another circuit is provided between X and Y,X and Y are functionally connected. The case where X and Y arefunctionally connected includes the case where X and Y are directlyconnected and X and Y are electrically connected.

Note that in this specification and the like, an explicit description “Xand Y are electrically connected” means that X and Y are electricallyconnected (i.e., the case where X and Y are connected with anotherelement or mother circuit provided therebetween), X and Y arefunctionally connected (i.e., the case where X and Y are functionallyconnected with another circuit provided therebetween), and X and Y aredirectly connected (i.e., the case where X and Y are connected withoutanother element or another circuit provided therebetween). That is, inthis specification and the like, the explicit description “X and Y areelectrically connected” is the same as the explicit description “X and Yare connected.”

For example, the case where a source (or a first terminal or the like)of a transistor is electrically connected to X through (or not through)Z1 and a drain (or a second terminal or the like) of the transistor iselectrically connected to Y through (or not through) Z2, or the casewhere a source (or a first terminal or the like) of a transistor isdirectly connected to part of Z1 and another part of Z1 is directlyconnected to X while a drain (or a second terminal or the like) of thetransistor is directly connected to part of Z2 and another part of Z2 isdirectly connected to Y, can be expressed by using any of the followingexpressions.

The expressions include, for example, “X, Y, a source (or a firstterminal or the like) of a transistor, and a drain (or a second terminalor the like) of the transistor are electrically connected to each other,and X, the source (or the first terminal or the like) of the transistor,the drain (or the second terminal or the like) of the transistor, and Yare electrically connected to each other in that order,” “a source (or afirst terminal or the like) of a transistor is electrically connected toX, a drain (or a second terminal or title like) of the transistor iselectrically connected to Y, and X, the source (or the first terminal orthe like) of the transistor, the drain (or the second terminal or thelike) of the transistor, and Y are electrically connected to each otherin that order,” and “X is electrically connected to Y through a source(or a first terminal or the like) and a drain (or a second terminal orthe like) of a transistor, and X, the source (or the first terminal orthe like) of the transistor, the drain (or the second terminal or thelike) of the transistor, and Y are connected in that order.” When theconnection order in a circuit structure is defined by an expressionsimilar to the above examples, a source (or a first terminal or thelike) and a drain (or a second terminal or the like) of a transistor canbe distinguished from each other to specify the technical scope.

Other examples of the expressions include “a source (or a first terminalor the like) of a transistor is electrically connected to X through atleast a first connection path, the first connection path does notinclude a second connection path, the second connection path is a pathbetween the source (or the first terminal or the like) of the transistorand a drain (or a second terminal or the like) of the transistor, Z1 ison the first connection path, the drain (or the second terminal or thelike) of the transistor is electrically connected to Y through at leasta third connection path, the third connection path does not include thesecond connection path, and Z2 is on the third connection path.” It isalso possible to use the expression “a source (or a first terminal orthe like) of a transistor is electrically connected to X through atleast Z1 on a first connection path, the first connection path docs notinclude a second connection path, the second connection path includes aconnection path through the transistor, a drain (or a second terminal orthe like) of the transistor is electrically connected to Y through atleast Z2 on a third connection path, and the third connection path doesnot include the second connection path.” Still another example of theexpression is “a source (or a first terminal or the like) of atransistor is electrically connected to X through at least Z1 on a firstelectrical path, the first electrical path does not include a secondelectrical path, the second electrical path is an electrical path fromthe source (or the first terminal or the like) of the transistor to adrain (or a second terminal or the like) of the transistor, the drain(or the second terminal or the like) of the transistor is electricallyconnected to Y through at least Z2 on a third electrical path, the thirdelectrical path docs not include a fourth electrical path, and thefourth electrical path is an electrical path from the drain (or thesecond terminal or the like) of the transistor to the source (or thefirst terminal or the like) of the transistor.” When the connection pathin a circuit structure is defined by an expression similar to the aboveexamples, a source (or a first terminal or the like) and a drain (or asecond terminal or the like) of a transistor can be distinguished fromeach other to specify the technical scope.

Note that these expressions are examples and there is no limitation onthe expressions. Here, X, Y, Z1, and Z2 each denote an object (e.g., adevice, an element, a circuit, a wiring, an electrode, a terminal, aconductive film, or a layer).

Even when independent components are electrically connected to eachother in a circuit diagram, one component has functions of a pluralityof components in some cases. For example, when part of a wiring alsofunctions as an electrode, one conductive film functions as the wiringand the electrode. Thus, the term “electrical connection” in thisspecification also means such a case where one conductive film hasfunctions of a plurality of components.

Unless otherwise specified, off-state current in this specificationrefers to drain current of a transistor in an off state (also referredto as a non-conductive state or a cutoff state). Unless otherwisespecified, the off state of an n-channel transistor means that adifference between gate voltage and source voltage (V_(gs)) is lowerthan the threshold voltage (V_(th)), and the off state of a p-channeltransistor means that V_(gs) is higher than V_(th). For example, theoff-state current of an n-channel transistor sometimes refers to draincurrent that flows when V_(gs) is lower than V_(th). The off-statecurrent of a transistor depends on V_(gs) in some cases. Thus, “theoff-state current of a transistor is lower than or equal to 10⁻²¹ A”means “there is V_(gs) with which the off-state current of a transistorbecomes lower than or equal to 10⁻²¹ A” in some cases. Furthermore, “theoff-state current of a transistor” means “off-state current in an offstate at predetermined V_(gs)”, off-state current in an off state V_(gs)at in a predetermined range”, “off-state current in an off state atV_(gs) with which sufficiently reduced off-state current is obtained”,or the like in some cases.

In this specification, the off-state current of a transistor withchannel width W is sometimes represented by a current value per givenchannel width (e.g., 1 μm). In that case, the off-state current may beexpressed in the unit with the dimension of current per length (e.g.,A/μm).

The off-state current of a transistor depends on temperature in somecases. Unless otherwise specified, the off-state current in thisspecification might be an off-state current at room temperature, 60° C.,85° C., 95° C., or 125° C. Alternatively, the off-state current might bean off-state current at temperature required for a semiconductor deviceor the like including the transistor or temperature at which asemiconductor device or the like including the transistor is used (e.g.,temperature in the range of 5° C. to 35° C.).

The off-state current of a transistor depends on voltage V_(ds) betweenits drain and source in some cases. Unless otherwise specified, theoff-state current in this specification might be off-state current atV_(ds), with an absolute value of 0.1 V, 0.8 V, 1 V, 12 V, 1.8 V, 2.5 V,3 V, 3.3 V, 10 V, 12 V, 16 V. or 20 V. Alternatively, the off-statecurrent might be an off-state current at V_(ds) required for asemiconductor device or the like including the transistor or V_(ds) usedin the semiconductor device or the like including the transistor.

One embodiment of the present invention can provide a currentmeasurement method capable of measuring an extremely low current. Oneembodiment of the present invention can provide an inspection method ofa semiconductor device utilizing the current measurement method. Oneembodiment of the present invention can provide a semiconductor deviceemploying the current measurement method. One embodiment of the presentinvention can provide a semiconductor device employing the inspectionmethod. One embodiment of the present invention can provide acharacteristic evaluation circuit. One embodiment of the presentinvention can provide a novel measurement method. One embodiment of thepresent invention can provide a novel semiconductor device.

Note that the description of these effects does not preclude theexistence of other effects. One embodiment of the present invention doesnot necessarily have all the effects listed above. Other effects will beapparent from and can be derived from the description of thespecification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating an example of a measurementsystem.

FIG. 2 is a flow chart showing an example of a measurement method.

FIG. 3 is a circuit diagram illustrating an example of a measurementsystem.

FIG. 4 illustrates an example of a measurement system.

FIG. 5 is a circuit diagram of an RC circuit.

FIG. 6 illustrates wave nature of electrons.

FIG. 7 illustrates electron traps assumed to be in a resistor.

FIGS. 8A to 8C are cross-sectional views illustrating a structureexample of a semiconductor device.

FIGS. 9A to 9D are a top view and cross-sectional views illustrating astructure example of a transistor.

FIGS. 10A and 10B are a cross-sectional view of a transistor and anenergy band diagram of the transistor.

FIGS. 11A to 11E are cross-sectional views illustrating a method formanufacturing a transistor.

FIGS. 12A to 12D are cross-sectional views illustrating a method formanufacturing a transistor.

FIG. 13 is a cross-sectional view illustrating a structure example of atransistor.

FIG. 14 is a cross-sectional view illustrating a structure example of atransistor.

FIG. 15 is a cross-sectional view illustrating a structure example of atransistor.

FIGS. 16A and 16B are a top view and a cross-sectional view illustratinga structure example of a transistor.

FIGS. 17A and 17B are circuit diagrams each illustrating an example of amemory device.

FIG. 18 is a block diagram illustrating an example of a CPU.

FIGS. 19A to 19F each illustrate an example of an electronic device.

FIGS. 20A to 20F each illustrate an example of an RF tag.

FIGS. 21A to 21D are Cs-corrected high-resolution TEM images of a crosssection of a CAAC-OS and a schematic cross-sectional view of theCAAC-OS.

FIGS. 22A to 22D are Cs-corrected high-resolution TEM images of a planeof a CAAC-OS.

FIGS. 23A to 23C show results of structural analysis of a CAAC-OS and asingle crystal oxide semiconductor by XRD.

FIGS. 24A and 24B show electron diffraction patterns of a CAAC-OS.

FIG. 25 shows changes in crystal parts of In—Ga—Zn oxides induced byelectron irradiation.

FIGS. 26A and 26B are schematic diagrams illustrating deposition modelsof a CAAC-OS and an nc-OS.

FIGS. 27A to 27C illustrate an InGaZnO₄ crystal and a pellet.

FIGS. 28A to 28D are schematic diagrams illustrating a deposition modelof a CAAC-OS.

FIG. 29 is a circuit diagram illustrating an example of a measurementsystem.

FIG. 30 is a circuit diagram of a prototyped circuit.

FIG. 31 is a cross-sectional view illustrating a device structure of aprototyped circuit.

FIG. 32 is a graph showing a change in potential V_(FN) of a retentionnode of a prototyped circuit over time.

FIG. 33 is a graph showing a stretched exponential function and anexponential function each describing a potential V_(FN).

FIG. 34 is a graph showing a stretched exponential function describingan off-state current of a transistor.

FIG. 35 is a graph showing parameter dependence of a stretchedexponential function describing a potential V_(FN).

FIG. 36 is a graph showing measured values of an off-state current of atransistor and an approximate straight line.

FIGS. 37A to 37C are graphs each throwing temperature dependence of astretched exponential function describing a potential V_(FN).

FIGS. 38A to 38C are graphs each showing temperature dependence of astretched exponential function describing an off-state current.

FIGS. 39A and 39B are graphs showing regression lines of the stretchedexponential functions in FIGS. 37A to 37C and FIGS. 38A to 38C.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments will be described with reference to drawings.However, the embodiments can be implemented with various modes. It willbe readily appreciated by those skilled in the art that modes anddetails can be changed in various ways without departing from the spiritand scope of the present invention. Thus, the present invention shouldnot be interpreted as being limited to the following description of theembodiments.

In the drawings, the size, the layer thickness, or the region isexaggerated for clarity in some cases. Therefore, embodiments of thepresent invention are not limited to such a scale. Note that drawingsare schematic views of ideal examples, and the embodiments of thepresent invention are not limited to the shape or the value illustratedin the drawings.

Embodiment 1

In this embodiment, examples of a current measurement method and acurrent measurement system of one embodiment of the present inventionwill be described with reference to FIG. 1 and FIG. 2. The configurationof the measurement system can be used as that of a characteristicevaluation circuit. Note that the measurement system described below isjust an example.

<<Measurement System>>

A circuit illustrated in FIG. 1 includes a transistor M0, a transistorM1, a capacitor C'S, a terminal WWL, a terminal WBL, a terminal RBL, anda terminal SL.

The circuit illustrated in FIG. 1 is a characteristic evaluation circuitused for measuring an off-state current of the transistor M0, which is atransistor under test (device under test: DUT). Note that an off-statecurrent is a current that flows between a source and a drain of atransistor when the transistor is off.

In FIG. 1, a gate of the transistor M0 is electrically connected to theterminal WWL, one of a source and a drain of the transistor M0 iselectrically connected to the terminal WBL, and the other of the sourceand the drain of the transistor M0 is electrically connected to a firstterminal of the capacitor CS.

In addition, in FIG. 1, a gate of the transistor M1 is electricallyconnected to the first terminal of the capacitor CS, one of a source anda drain of the transistor M1 is electrically connected to the terminalRBL, and the other of the source and the drain of the transistor M1 iselectrically connected to the terminal SL.

In FIG. 1, a low potential is supplied to a second terminal of thecapacitor CS. The low potential may be, for example, a ground potential.

In FIG. 1, a node where the other of the source and the drain of thetransistor M0, the gate of the transistor M1, and the first terminal ofthe capacitor CS are electrically connected to each other is referred toas a node FN. When the transistor M0 is turned off, the node FN becomeselectrically floating.

Hereinafter, a method for measuring the off-state current of thetransistor M0 will be described. Although the transistor M0 and thetransistor M1 will be described as n-channel transistors below, thisembodiment is also applicable to the case where the transistor M0 or thetransistor M1 is a p-channel transistor.

<<Measurement Method>>

FIG. 2 is a flow chart showing a method for measuring the off-statecurrent of the transistor M0.

<Step 1>

First, the transistor M0 is turned on so that a potential is written tothe node FN, and a current that flows between the source and the drainof the transistor M1 at that time is measured. This is repeated fordifferent potentials to determine the correspondence between thepotentials written to the node FN and values of currents flowing in thetransistor M1.

To determine the correspondence between potentials and currents, forexample, a current that flows between the terminal RBL and the terminalSL is measured while 3 V, 1.1 V, 0 V (ground potential), and 0 V areapplied to the terminal WWL, the terminal RBL, the terminal SL, and thesecond terminal of the capacitor CS, respectively, with potentialsapplied to the terminal WBL in increments of 0.1 V from 0 V to 1 V.

<Step 2>

The transistor M0 is turned on to write a charge to the node FN. At thistime, the transistor M1 is also turned on and a current (on-statecurrent) flows between the source and the drain of the transistor M1.Here, for example, 3 V, 1.1 V, 1.1 V, 0 V, and 0 V are applied to theterminal WWL, the terminal WBL, the terminal RBL, the terminal SL, andthe second terminal of the capacitor CS, respectively.

<Step 3>

Next, the transistor M0 is turned off to make the node FN electricallyfloating. As a result, the charge of the node FN is retained and thetransistor M1 is kept on. Here, for example, −1 V, 0 V, 1.1 V, 0 V, and0 V are applied to the terminal WWL, the terminal WBL, the terminal RBL,the terminal SL, and the second terminal of the capacitor CS,respectively.

<Step 4>

Then, while the transistor M0 is kept off, a current that flows betweenthe source and the drain of the transistor M1 is measured for a certainperiod to generate data on the correspondence between currents andmeasuring time. Note that the measuring time is time elapsed after thetransistor M0 is turned off in Step 3. The measuring time is set greaterthan or equal to 5×10² seconds and less than or equal to 1×10⁵ seconds,greater than or equal to 1×10³ seconds and less than or equal to 1×10⁴seconds, or greater than or equal to 1×10³ seconds and less than orequal to 5×10³ seconds.

<Step 5>

With the use of the correspondence between potentials and currentsdetermined in Step 1, data on the correspondence between a potentialV_(FN) of the node FN and Time t is generated. Note that “Time t” inthis specification expresses the measuring time.

<Step 6>

A stretched exponential function represented by Formula (1) is fitted tothe data obtained in Step 5 to determine parameters α, β, and τ inFormula (1).

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 3} \right\rbrack & \; \\{{V_{FN}(t)} = {\alpha \times e^{- {(\frac{t}{\tau})}^{\beta}}}} & (1)\end{matrix}$

<Step 7>

Lastly, the off-state current of the transistor M0 is calculated withthe use of α, β, and τ determined in Step 6.

The derivative of both sides of Formula (0.1) with respect to time givesFormula (2).

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 4} \right\rbrack & \; \\{\frac{{dV}_{FN}}{dt} = {{- \frac{\alpha \times \beta}{\tau^{\beta}}} \times t^{\beta - 1} \times e^{- {(\frac{t}{\tau})}^{\beta}}}} & (2)\end{matrix}$

An off-state current I_(OFF) of the transistor M0, capacitance C_(S) ofthe capacitor CS, and the potential V_(FN) of the node FN satisfy thefollowing relational expression.

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 5} \right\rbrack & \; \\{{I_{OFF}(t)} = {C_{S} \times \frac{{dV}_{FN}}{dt}}} & (3)\end{matrix}$

Substitution of Formula (3) into Formula (2) gives the followingformula.

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 6} \right\rbrack & \; \\{{I_{OFF}(t)} = {C_{S} \times \frac{\alpha \times \beta}{\tau^{\beta}} \times t^{\beta - 1} \times e^{- {(\frac{t}{\tau})}^{\beta}}}} & (4)\end{matrix}$

Substitution of α, β, and τ determined in Step 6 into Formula (4) allowsthe calculation of the off-state current of the transistor M0.

In the above manner, the off-state current of the transistor M0 can bemeasured using the measurement method shown in FIG. 2.

Here, a circuit illustrated in FIG. 29 is discussed.

The circuit illustrated in FIG. 29 is a circuit excluding the transistorM1 from the circuit illustrated in FIG. 1.

In the case where a wide band gap semiconductor such as an oxidesemiconductor is used for the transistor M0, for example, the off-statecurrent of the transistor M0 is too low to actually measure withmeasurement equipment.

Also in the case where a minute transistor whose channel width issmaller than 100 ran is used as the transistor M0, for example, theoff-state current of the transistor M0 is too low to actually measurewith measurement equipment.

To measure the off-state current of the transistor M0 of the circuitillustrated in FIG. 29, a current that flows in the terminal WBL ismeasured; however, it is difficult to actually measure the current thatflows in the terminal WBL when the off-state current of the transistorM0 is extremely low as described above.

Thus, in the case where the off-state current of the transistor M0 isextremely low, a method with which the off-state current of thetransistor M0 is measured using the on-state current of the transistorM1 as described with reference to FIG. 1 is very effective.

The extremely low off-state current of the transistor M0 can lead tolong-term retention of the charge written to the node FN. This featureenables the circuit illustrated in FIG. 1 (or FIG. 29) to be applied toa memory element such as a nonvolatile memory.

The off-state current of the transistor M0 several months to severalyears ahead can be estimated using the measurement method shown in FIG.2. Thus, long-term charge retention characteristics can be estimatedwhen the circuit illustrated in FIG. 1 (or FIG. 29) is applied to amemory element.

The characteristic evaluation circuit illustrated in FIG. 1 may includea transistor M2 as illustrated in FIG. 3. A gate of the transistor M2 iselectrically connected to a terminal RWL. The terminal RWL has afunction of supplying a signal with which the transistor M2 is turned onor off.

<<Measurement Environment≥≥

A measurement sample including a characteristic evaluation circuit maybe put in an inert oven in which temperature is kept constant, asillustrated in FIG. 4. In addition, a constant-temperature air generatormay be used to make the temperature of an atmosphere around measurementequipment, constant. The measurement environment is controlled asdescribed above, whereby an adverse effect of noise caused by atemperature change can be reduced.

Specifically, a sample 210 is put in an inert oven 200 and thetemperature of the sample 210 is kept constant. The humidity in theinert oven 200 can be reduced by supplying dry air 220 to the inert oven200 at that time, which provides a low-humidity measurement environment.The sample 210 is connected to a transit portion 231 with a flat cable232. The transit portion 231 is connected to measurement equipment 241and measurement equipment 242 with a coaxial cable 251 and a coaxialcable 252, respectively. The measurement equipment 242 sends a signalfor transmitting data of the sample 210 to the transit portion 231. Thedata of the sample 210 is supplied from the transit portion 231 to themeasurement equipment 241. Note that a measurement system (including thesample and the measurement equipment) is preferably kept at a constanttemperature. In order to keep the measurement system at a constanttemperature, for example, the measurement system is covered by a heatinsulator 260, a plastic corrugated cardboard, or the like, andconstant-temperature air is supplied using a constant-temperature airgenerator 270 and a duct cable 280. It is preferable that themeasurement system not be entirely covered by the heat insulator 260,the plastic corrugated cardboard, or the like so that a small amount ofconstant-temperature air can flow off to the outside.

<<Stretched Exponential Function>>

Next, the stretched exponential function represented by Formula (1) willbe described.

A circuit consisting of a resistor R and a capacitor C (RC circuit) asillustrated in FIG. 5 is described, for example. A current I flowing inthis circuit can be represented by Formula (5).

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 7} \right\rbrack & \; \\{{I(t)} = {\frac{V}{R} \times e^{- \frac{i}{CR}}}} & (5)\end{matrix}$

A current that can be measured by measurement equipment, such as thecurrent I represented by Formula (5), is regarded as the flow of a largenumber of electrons, and the behavior of the electrons can be explainedby the classical theory, for example.

In contrast, a current that is too low to measure by measurementequipment is regarded as the flow of an extremely small number ofelectrons. In some cases, such an extremely low current is regarded asthe flow of several to several tens of electrons. To explain the flow ofsuch an extremely small number of electrons, it is preferable to use thequantum theory or the statistical mechanics.

In the quantum theory, for example, a state of an electron isrepresented by the wave function Ψ, and the position r of an electron isrepresented by the existence probability P (see FIG. 6).

In the case where the extremely low current flows in the RC circuit inFIG. 5, the behavior of electrons needs to be explained by the quantumtheory. For this reason, it is assumed that traps exist in the resistorR in accordance with a certain function and electrons are trapped by thetraps. The assumed traps will be described below with reference to FIG.7.

In FIG. 7, n traps (n is an integer greater than or equal to 1)represented by traps Tr₁ to Tr_(n) exist in the resistor R. The trapsTr₁ to Tr_(n) are distributed one-dimensionally with a length x in therange from 0 to a. It is assumed that each trap has a length of 2l₀.

Electrons are assumed to be trapped by the traps in the resistor R inaccordance with the existence probability P₁(t). Note that the existenceprobability P₁(t) has a physical meaning of the probability of anelectron being trapped by the trap Tr₁ during Time t.

It is assumed that the traps Tr₁ to Tr_(n) in the resistor R can berepresented by the distribution function ρ(x)=1/a. The formula at Timet₁ is as follows. Note that x₀ in Formula (6) represents the coordinateof the position where an electron is trapped.

[Formula 8]

P ₁(t ₁)=∫_(x=0) ^(a) dxp(x)P ₁(t ₁ ,x−x ₀)  (6)

A diffusion constant D of an electron is introduced. With the use of theChandrasekhar equation of diffusion probability (see Non-patent Document1), the integration in Formula (6) can be developed as follows.

$\begin{matrix}{\mspace{79mu} \left\lbrack {{Formula}\mspace{14mu} 9} \right\rbrack} & \; \\{{P_{1}\left( t_{1} \right)} = {\frac{1}{a}\left( \frac{D}{\pi \; t_{1}} \right)^{\frac{1}{2}}\left\{ {2 - {\exp \left( {{{- x_{0}^{2}}/4}{Dt}_{1}} \right)} - {\exp \left\lbrack {{{- \left( {a - x_{0}} \right)^{2}}/4}{Dt}_{1}} \right\rbrack}} \right\}}} & (7)\end{matrix}$

In Formula (7), x₀ and (a−x₀) are sufficiently larger than Dt₁. Thus,the existence probability P₁(t₁) at Time t₁ can be represented by thefollowing formula.

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 10} \right\rbrack & \; \\{{P_{1}\left( t_{1} \right)} = {\frac{2}{a}\left( \frac{D}{\pi \; t_{1}} \right)^{1/2}}} & (8)\end{matrix}$

The integration of Formula (8) with respect to time gives Formula (9).Formula (9) represents the existence probability of electrons trappedduring Time t.

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 11} \right\rbrack & \; \\{{P_{1}(t)} = {\frac{4}{a}\left( \frac{Dl}{\pi} \right)^{1/2}}} & (9)\end{matrix}$

The probability of an electron moving in the resistor R without beingtrapped by the trap Tr₁ is represented by [1−P₁(t)]. Accordingly, theprobability of an electron moving in the resistor R without beingtrapped by any trap is represented by Formula (10).

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 12} \right\rbrack & \; \\{{1 - {P(t)}} = {{{1 - {P_{1}(t)}}}^{n} = \left\lbrack {1 - {\frac{4}{a}\left( \frac{Dl}{\pi} \right)^{1/2}}} \right\rbrack^{n}}} & (10)\end{matrix}$

The limit of n is described. As apparent from FIG. 7, a=n×2l₀ issatisfied; thus, Formula (11) is obtained.

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 13} \right\rbrack & \; \\{{\lim_{n\rightarrow\infty}{{1 - {P(t)}}}} = {\lim_{n\rightarrow\infty}\left\lbrack {1 - {\frac{2}{{nI}_{0}}\left( \frac{Dl}{\pi} \right)^{1/2}}} \right\rbrack^{n}}} & (11)\end{matrix}$

The generic form of the exponential function with respect to the limitgives Formula (12).

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 14} \right\rbrack & \; \\{{\lim_{n\rightarrow\infty}\left( {1 + \frac{x}{n}} \right)^{n}} = e^{x}} & (12)\end{matrix}$

Formula (11) and Formula (12) give Formula (13).

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 15} \right\rbrack & \; \\{{1 - {P(t)}} = {A_{0} \times {\exp \left\lbrack {- \left( \frac{t}{\tau} \right)^{1/2}} \right\rbrack}}} & (13)\end{matrix}$

Formula (13) represents the probability of an electron passing throughthe resistor R without being trapped by traps. Note that Formula (13) isthe stretched exponential function in the case where β in Formula (1) is½.

The behavior of electrons is explained by the quantum theory asdescribed above, whereby the stretched exponential function that is usedfor the calculation of the off-state current of the transistor M0 can beobtained. This means that an extremely low current such as the off-statecurrent can be explained by the quantum theory or the statisticalmechanics and is preferably calculated using the stretched exponentialfunction in Formula (4).

The structures, methods, and the like described in this embodiment canbe used as appropriate in combination with any of the structures,methods, and the like described in other embodiments.

Embodiment 2

In this embodiment, an example of a semiconductor device applicable tothe measurement system illustrated in FIG. 1 will be described.

<<Cross-Sectional View of Semiconductor Device>

FIG. 8A is a cross-sectional view of a semiconductor device of oneembodiment of the present invention. The semiconductor deviceillustrated in FIG. 8A includes a substrate 701, the transistor M0, thetransistor M1, the capacitor CS, an element isolation layer 702, aninsulating film 703, a conductive film 704, a conductive film 705, aconductive film 706, a plug 707, a plug 708, and a plug 709. Thetransistor M1 includes impurity regions 721 serving as source/drainregions, a gate electrode 723, a gate insulating film 724, and asidewall insulating layer 725.

The semiconductor device illustrated in FIG. 8A includes the transistorM1 containing a first semiconductor material in a lower portion and thetransistor M0 containing a second semiconductor material in an upperportion. FIG. 8A illustrates cross-sectional views of the transistor M0and the transistor M1 in a channel length direction.

The first and second semiconductor materials preferably have differentband gaps. For example, the first semiconductor material can be asemiconductor material other than an oxide semiconductor (examples ofsuch a semiconductor material include silicon, germanium, silicongermanium, silicon carbide, and gallium arsenide), and the secondsemiconductor material can be an oxide semiconductor. A transistor usingsingle crystal silicon as the first semiconductor material can operateat high speed easily. In contrast, a transistor including an oxidesemiconductor as the second semiconductor material has a low off-statecurrent.

The details of the transistor M0 will be described in Embodiment 3.

The transistor M1 may be either an n-channel transistor or a p-channeltransistor; an appropriate transistor is used depending on a circuit.Furthermore, the specific structure of the semiconductor device, such asthe material or the structure used for the semiconductor device, is notnecessarily limited to those described here except for the use of thetransistor of one embodiment of the present invention which includes anoxide semiconductor.

The transistor M1 may be provided with an impurity region serving as alightly doped drain (LDD) region or an extension region under thesidewall insulating layer 725. In particular, when the transistor M1 isan n-channel transistor, the LDD region or the extension region ispreferably provided in order to suppress the deterioration due to hotcarriers.

As the transistor M1, a transistor containing silicide (salicide) or atransistor that docs not include the sidewall insulating layer 725 maybe used. When a structure that contains silicide (salicide) is used, theresistance of the source region and the drain region can be furtherlowered and the speed of the semiconductor device can be increased.Furthermore, the semiconductor device can operate at a low voltage;thus, power consumption of the semiconductor device can be reduced.

Since the two kinds of transistors are stacked, the area occupied by thecircuit can be reduced, allowing a plurality of circuits to be highlyintegrated.

The capacitor CS and the transistor M0 can be formed in the sameprocess. Although the capacitor CS and the transistor M0 are provided inthe same tier in FIG. 8A, the capacitor CS may be provided in the sametier as the transistor M1. Alternatively, the capacitor CS may beprovided in a tier between the transistor M1 and the transistor M0, orin a tier over the transistor M1 and the transistor M0.

As the substrate 701, a single crystal semiconductor substrate or apolycrystalline semiconductor substrate made of silicon or siliconcarbide, a compound semiconductor substrate made of silicon germanium, asilicon on insulator (SOI) substrate, or the like may be used. Atransistor formed using a semiconductor substrate can easily operate athigh speed. In the case of using a p-type single crystal siliconsubstrate as the substrate 701, an impurity element imparting n-typeconductivity may be added to part of the substrate 701 to form ann-well, and a p-type transistor can be formed in a region where then-well is formed. As the impurity element imparting n-type conductivity,phosphorus (P), arsenic (As), or the like can be used. As the impurityelement imparting p-type conductivity, boron (B) or the like may beused.

Alternatively, the substrate 701 may be a metal substrate or aninsulating substrate provided with a semiconductor film. Examples of themetal substrate are a stainless steel substrate, a substrate includingstainless steel foil, a tungsten substrate, and a substrate includingtungsten foil. Examples of the insulating substrate are a glasssubstrate, a quartz substrate, a plastic substrate, a flexiblesubstrate, an attachment film, paper including a fibrous material, and abase film. Examples of the glass substrate are a barium borosilicateglass substrate, an aluminoborosilicate glass substrate, and a soda limeglass substrate. Examples of the flexible substrate are flexiblesynthetic resin substrates such as substrates of plastics typified bypolyethylene terephthalate (PET), polyethylene naphthalate (PEN), andpolyether sulfone (PES) and an acrylic substrate. Examples of theattachment film are attachment films formed using polypropylene,polyester, polyvinyl fluoride, polyvinyl chloride, and the like.Examples of the base film are base films formed using polyester,polyamide, polyimide, aramid, epoxy, an inorganic vapor deposition film,and paper.

Alternatively, a semiconductor element may be formed using one substrateand then be transferred to another substrate. Examples of a substrate towhich a semiconductor element is transferred include, in addition to theabove-described substrates, a paper substrate, a cellophane substrate,an aramid film substrate, a polyimide film substrate, a stone substrate,a wood substrate, a cloth substrate (including a natural fiber (e.g.,silk, cotton, or hemp), a synthetic fiber (e.g., nylon, polyurethane, orpolyester), a regenerated fiber (e.g., acetate, cupra, rayon, orregenerated polyester), or the like), a leather substrate, and a rubbersubstrate. With the use of these substrates can reduce the weight or thethickness of a semiconductor device.

The transistor M1 is isolated from other transistors formed on thesubstrate 701 by the element isolation layer 702. The element isolationlayer 702 can be formed using an insulator containing one or morematerials selected from aluminum oxide, aluminum oxynitride, magnesiumoxide, silicon oxide, silicon oxynitride, silicon nitride oxide, siliconnitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide,lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and thelike.

Here, in the case where a silicon-based semiconductor material is usedfor the transistor M1 provided in a lower tier, hydrogen in aninsulating layer provided in the vicinity of the semiconductor layer ofthe transistor M1 terminates dangling bonds of silicon; accordingly, thereliability of the transistor M1 can be improved. Meanwhile, in the casewhere an oxide semiconductor is used for the transistor M0 provided inan upper tier, hydrogen in an insulating layer provided in the vicinityof the semiconductor layer of the transistor M0 becomes a factor ofgenerating carriers in the oxide semiconductor, thus, the reliability ofthe transistor M0 might be decreased. Therefore, in the case where thetransistor M0 formed using an oxide semiconductor is provided over thetransistor M1 formed using a silicon-based semiconductor material, it isparticularly effective that the insulating film 703 having a function ofpreventing diffusion of hydrogen is provided between the transistors M0and M1. The insulating film 703 makes hydrogen remain in the lower tier,thereby improving the reliability of the transistor M1. In addition,since the insulating film 703 suppresses diffusion of hydrogen from thelower tier to the upper tier, the reliability of the transistor M0 canalso be improved.

The insulating film 703 can be formed using, for example, aluminumoxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttriumoxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, oryttria-stabilized zirconia (YSZ).

The conductive films 704 to 706 preferably have a single-layer structureor a stacked-layer structure of a conductive film containing alow-resistance material selected from copper (Cu), tungsten (W),molybdenum (Mo), gold (Au), aluminum (At), manganese (Mn), titanium(Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn),iron (Fc), and cobalt (Co), an alloy of such a low-resistance material,or a compound containing such a material as its main component. It isparticularly preferable to use a high-melting-point material which hasboth heat resistance and conductivity, such as tungsten or molybdenum.In addition, the plugs are preferably formed using a low-resistanceconductive material such as aluminum or copper. The plugs are furtherpreferably formed using a Cu—Mn alloy, in which case manganese oxideformed at the interface with an insulator containing oxygen has afunction of preventing Cu diffusion.

The plugs 707 to 709 preferably have a single-layer structure or astacked-layer structure of a conductive film containing a low-resistancematerial selected from copper (Cu), tungsten (W), molybdenum (Mo), gold(Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta),nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), and cobalt(Co), an alloy of such a low-resistance material, or a compoundcontaining such a material as its main component. It is particularlypreferable to use a high-melting-point material which has both heatresistance and conductivity, such as tungsten or molybdenum. Inaddition, the wirings are preferably formed using a low-resistanceconductive material such as aluminum or copper. The wirings are furtherpreferably formed using a Cu—Mn alloy, in which case manganese oxideformed at the interface with an insulator containing oxygen has afunction of preventing Cu diffusion.

In FIG. 8A, regions without reference numerals and hatch patternsrepresent regions formed of an insulator. The regions can be formedusing an insulator containing at least one of aluminum oxide, aluminumnitride oxide, magnesium oxide, silicon oxide, silicon oxynitride,silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide,yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide,hafnium oxide, tantalum oxide, and the like. Alternatively, for theregions, an organic resin such as a polyimide resin, a polyamide resin,an acrylic resin, a siloxane resin, an epoxy resin, or a phenol resincan be used.

A transistor 750 illustrated in FIGS. 8B and 8C may be used as thetransistor M1. FIG. 8C illustrates a cross section along dashed-dottedline E-F in FIG. 8B. The transistor 750 formed over a semiconductorsubstrate 730 includes a semiconductor layer 756 where a channel isformed, an impurity region 751, an impurity region 755, a gateinsulating film 753, a gate electrode 752, a sidewall insulating layer754, and an element isolation layer 731. The semiconductor layer 756 hasa protrusion, and the gate insulating film 753 and the gate electrode752 are provided along top and side surfaces of the protrusion. Such atransistor is also referred to as a FIN transistor because it utilizes aprotrusion of a semiconductor substrate. Note that an insulating filmserving as a mask for forming the protrusion may be provided in contactwith the top of the protrusion. Although foe case where the protrusionis formed by processing a portion of the semiconductor substrate 730 isdescribed here, a semiconductor layer having a protruding shape may beformed by processing an SOI substrate.

Although channel regions of the transistors M0 and M1 in FIG. 8A containdifferent semiconductor materials, the channel regions of thetransistors M0 and M1 may contain the same semiconductor material. Forexample, the channel regions of the transistors M0 and M1 may bothcontain an oxide semiconductor.

The structures, methods, and the like described in this embodiment canbe used as appropriate in combination with any of the structures,methods, and the like described in other embodiments.

Embodiment 3

In this embodiment, examples of a transistor that can be used as thetransistor M0 described in Embodiments 1 and 2 are described.

<<Structure Example 1 of Transistor>>

FIGS. 9A to 9D are a top view and cross-sectional views of a transistor600. FIG. 9A is the top view. FIG. 9B illustrates a cross section alongdashed-dotted line Y1-Y2 in FIG. 9A. FIG. 9C illustrates a cross sectionalong dashed-dotted line X1-X2 in FIG. 9A. FIG. 9D illustrates a crosssection along dashed-dotted line X3-X4 in FIG. 9A. In FIGS. 9A to 9D,some components are scaled up or down or omitted for easy understanding.In some cases, the direction of the dashed-dotted line Y1-Y2 is referredto as a channel length direction and the direction of the dashed-dottedline X1-X2 is referred to as a channel width direction.

Note that the channel length refers to, for example, a distance betweena source (source region or source electrode) and a drain (drain regionor drain electrode) in a region where a semiconductor (or a portionwhere a current flows in a semiconductor when a transistor is on) and agate electrode overlap with each other or a region where a channel isformed in a top view of the transistor. In one transistor, channellengths in all regions are not necessarily the same. In other words, thechannel length of one transistor is not limited to one value in somecases. Therefore, in this specification, foe channel length is any oneof values, the maximum value, the minimum value, or the average value ina region where a channel is formed.

The channel width refers to, for example, the length of a portion wherea source and a drain face each other in a region where a semiconductor(or a portion where a current flows in a semiconductor when a transistoris on) and a gate electrode overlap with each other, or a region where achannel is formed. In one transistor, channel widths in all regions arenot necessarily the same. In other words, the channel width of onetransistor is not limited to one value in some cases. Therefore, in thisspecification, the channel with is any one of values, the maximum value,the minimum value, or the average value in a region where a channel isformed.

Note that depending on transistor structures, a channel width in aregion where a channel is actually formed (hereinafter referred to as aneffective channel width) is different from a channel width shown in atop view of a transistor (hereinafter referred to as an apparent channelwidth) in some cases. For example, in a transistor having athree-dimensional structure, an effective channel width is greater thanan apparent channel width shown in a top view of the transistor, and itsinfluence cannot be ignored in some cases. For example, in aminiaturized transistor having a three-dimensional structure, theproportion of a channel region formed in a side surface of asemiconductor is high in some cases. In that case, an effective channelwidth obtained when a channel is actually formed is greater than anapparent channel width shown in the top view.

In a transistor having a three-dimensional structure, an effectivechannel width is difficult to measure in some cases. For example,estimation of an effective channel width from a design value requires anassumption that the shape of a semiconductor is known. Therefore, in thecase where the shape of a semiconductor is not known accurately, it isdifficult to measure an effective channel width accurately.

Therefore, in this specification, in a top view of a transistor, anapparent channel width that is a length of a portion where a source anda drain face each other in a region where a semiconductor and a gateelectrode overlap with each other is referred to as a surrounded channelwidth (SCW) in some cases. Furthermore, in this specification, in thecase where the term “channel width” is simply used, it may denote asurrounded channel width and an apparent channel width. Alternatively,in this specification, in the case where the term “channel width” issimply used, it may denote an effective channel width in some cases.Note that the values of a channel length, a channel width, an effectivechannel width, an apparent channel width, a surrounded channel width,and the like can be determined by obtaining and analyzing across-sectional TEM image and the like.

Note that in the case where field-effect mobility, a current value perchannel width, and the like of a transistor are obtained by calculation,a surrounded channel width may be used for the calculation. In thatcase, the values may be different from those calculated using aneffective channel width in some cases.

The transistor 600 includes a substrate 640; an insulating film 651 overthe substrate 640; a conductive film 674 over the insulating film 651;an insulating film 656 over the insulating film 651 and the conductivefilm 674; an insulating film 652 over the insulating film 656; asemiconductor 661 and a semiconductor 662 stacked over the insulatingfilm 652 in this order, a conductive film 671 and a conductive film 672in contact with a top surface of the semiconductor 662; a semiconductor663 in contact with the semiconductor 661, the semiconductor 662, theconductive film 671, and the conductive film 672; an insulating film 653and a conductive film 673 over the semiconductor 663; an insulating film654 over the conductive film 673 and the insulating film 653; and aninsulating film 655 over the insulating film 654. Note that thesemiconductors 661, 662, and 663 are collectively referred to as asemiconductor 660.

The conductive film 671 has a function as a source electrode of thetransistor 600. The conductive film 672 has a function as a drainelectrode of the transistor 600.

The conductive film 673 has a function as a first gate electrode of thetransistor 600.

The insulating film 653 has a function as a first gate insulating filmof the transistor 600.

The conductive film 674 has a function as a second gate electrode of thetransistor 600.

The insulating films 656 and 652 have a function as a second gateinsulating film of the transistor 600.

Potentials applied to the conductive films 673 and 674 may be the sameor different from each other. Note that the conductive film 674 isunnecessary in some cases.

As illustrated in FIG. 9C, a side surface of the semiconductor 662 issurrounded by the conductive film 673. With such a structure, thesemiconductor 662 can be electrically surrounded by an electric field ofthe conductive film 673 (a transistor structure in which a semiconductoris electrically surrounded by an electric field of a conductive film(gate electrode) is referred to as a surrounded channel (s-channel)structure). Therefore, a channel is formed in the entire semiconductor662 (bulk) in some cases. In the s-channel structure, a large amount ofcurrent can flow between a source and a drain of a transistor, so that ahigh current in an on state (on-state current) can be achieved. Thes-channel structure enables a transistor to operate at high frequency.

The s-channel structure, because of its high on-state current, issuitable for a semiconductor device such as large-scale integration.(LSI) which requires a miniaturized transistor. A semiconductor deviceincluding the miniaturized transistor can have a high integration degreeand high density. The transistor preferably has, for example, a regionwhere a channel length is greater than or equal to 10 nm and less than 1μm, further preferably greater than or equal to 10 nm and less than 100nm, still further preferably greater than or equal to 10 nm and lessthan 70 nm, yet still further preferably greater than or equal to 10 nmand less than 60 nm, and yet still further preferably greater than orequal to 10 nm and less than 30 nm. In addition, the transistorpreferably has, for example, a region where a channel width is greaterthan or equal to 10 nm and less than 1 μm, further preferably greaterthan or equal to 10 nm and less than 100 nm, still further preferablygreater than or equal to 10 nm and less than 70 nm, yet still furtherpreferably greater than or equal to 10 nm and less than 60 nm, and yetstill further preferably greater than or equal to 10 nm and less than 30nm.

Furthermore, the s-channel structure is suitable for a transistor thatneeds to operate at high frequency because of its high on-state current.A semiconductor device including the transistor can operate at highfrequency.

In addition, the s-channel structure is suitable for a power controltransistor because of its high on-state current. To employ the s-channelstructure in the power control transistor that requires a high withstandvoltage and high current, the channel length and the channel width arepreferably long. For example, the transistor preferably has a regionwhere the channel length is longer than or equal to 1 μm, furtherpreferably longer than or equal to 10 μm, and still further preferablylonger than or equal to 100 μm. In addition, the transistor preferablyhas a region where the channel width is longer than or equal to 1 μm,further preferably longer than or equal to 10 μm, and still furtherpreferably longer than or equal to 100 μm. Here, the transistor has aregion where the channel length is smaller than 1 cm and a region wherethe channel width is smaller than 1 cm.

The insulating film 651 has a function of electrically isolating thesubstrate 640 and the conductive film 674 from each other.

The insulating film 652 preferably includes an oxide. In particular, theinsulating film 652 preferably includes an oxide material from whichpart of oxygen is released by heating. The insulating film 652preferably includes an oxide containing oxygen in excess of that in thestoichiometric composition. Part of oxygen is released by heating fromthe oxide film containing oxygen in excess of that in the stoichiometriccomposition. Oxygen released from the insulating film 652 is supplied tothe semiconductor 660 that is an oxide semiconductor, so that oxygenvacancies in the oxide semiconductor can be reduced. Consequently,changes in the electrical characteristics of the transistor can bereduced and the reliability of the transistor can be improved.

The oxide film containing oxygen in excess of that in the stoichiometriccomposition is an oxide film of which the amount of released Oxygenconverted into oxygen atoms is greater than or equal to 1.0×10¹⁸atoms/cm³, preferably greater than or equal to 3.0×10²⁰ atoms/cm³ inthermal desorption spectroscopy (TDS) analysis, for example. Note thatthe temperature of the film surface in the TDS analysis is preferablyhigher than or equal to 100° C. and lower than or equal to 700° C., orhigher than or equal to 100° C. and lower than or equal to 500° C.

The insulating film 656 has a function of preventing oxygen contained inthe insulating film 652 from decreasing by bonding to metal contained inthe conductive film 674.

The insulating film 654 has a function of blocking oxygen, hydrogen,water, alkali metal, alkaline earth metal, and the like. Providing theinsulating film 654 can prevent outward diffusion of oxygen from thesemiconductor 660 and entry of hydrogen, water, or the like into thesemiconductor 660 from the outside.

<Semiconductor>

Next, semiconductors which can be used as foe semiconductors 661 to 663or the like will be described below.

In the transistor 600, it is preferable that the current flowing betweena source and drain in an off state (off-state current) be low. Here, theterm “low off-state current” means that normalized off-state current permicrometer of channel width at room temperature with a source-drainvoltage of 10 V is lower than or equal to 10×10⁻²¹ A. An example of atransistor with such a low off-state current is a transistor includingan oxide semiconductor as a semiconductor.

The semiconductor 662 is, for example, an oxide semiconductor containingindium (In). The semiconductor 662 has a high carrier mobility (electronmobility) when containing, for example, indium. The semiconductor 662preferably contains an element M. The element M is preferably aluminum(Al), gallium (Ga), yttrium (Y), tin (Sn), or the like. Other elementswhich can be used as the element M include boron (B), silicon (Si),titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr),molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium(Hf), tantalum (Ta), and tungsten (W). Note that two or more of theabove elements may be used in combination as the element M. The elementM is an element having high bonding energy with oxygen, for example. Theelement M is an element whose bonding energy with oxygen is higher thanthat of indium. The element M is an element that can increase the energygap of the oxide semiconductor, for example. Furthermore, thesemiconductor 662 preferably contains zinc (Zn). When the oxidesemiconductor contains zinc, the oxide semiconductor is easilycrystallized in some cases.

Note that the semiconductor 662 is not limited to the oxidesemiconductor containing indium. The semiconductor 662 may be, forexample, an oxide semiconductor which does not contain indium andcontains zinc, an oxide semiconductor which does not contain indium andcontains gallium, or an oxide semiconductor which does not containindium and contains tin, e.g., a zinc tin oxide or a gallium tin oxide.

For the semiconductor 662, an oxide with a wide energy gap may be used.For example, the energy gap of the semiconductor 662 is greater than orequal to 2.5 eV and less than or equal to 4.2 eV, preferably greaterthan or equal to 2.8 eV and less than or equal to 3.8 eV, morepreferably greater than or equal to 3 eV and less than or equal to 3.5eV.

The semiconductor 662 preferably includes a CAAC-OS film which will bedescribed later.

For example, the semiconductor 661 and the semiconductor 663 include oneor more, or two or more elements other than oxygen included in thesemiconductor 662. Since the semiconductor 661 and the semiconductor 663each include one or more, or two or more elements other than oxygenincluded in the semiconductor 662, an interface state is less likely tobe formed at the interface between the semiconductor 661 and thesemiconductor 662 and the interface between the semiconductor 662 andthe semiconductor 663.

Note that in the case of using an In-M-Zn oxide as the semiconductor661, when the summation of In and M is assumed to be 100 atomic %, theproportions of In and M are preferably set to be less than 50 atomic %and greater than 50 atomic %, respectively, more preferably less than 25atomic % and greater than 75 atomic %, respectively. In the case wherethe semiconductor 661 is formed by a sputtering method, a sputteringtarget with the above composition, for example, a sputtering targetcontaining In, M, and Zn at an atomic ratio of 1:3:2, is preferablyused.

In the case where an In-M-Zn oxide is used for the semiconductor 662 andthe summation of In and hi is assumed to be 100 atomic %, theproportions of In and M are preferably set to be greater than 25 atomic% and less than 75 atomic %, respectively, and more preferably greaterthan 34 atomic % and less than 66 atomic %, respectively. In the casewhere the semiconductor 662 is formed by a sputtering method, asputtering target with the above composition, for example, a sputteringtarget containing In, M, and Zn at an atomic ratio of 1:1:1, 1:1:1.2,2:1:3, 3:1:2, or 4:2:4.1, is preferably used. In particular, when asputtering target containing In, Ga, and Zn at an atomic ratio of4:2:4.1 is used, the semiconductor 662 may contain In, Ga, and Zn at anatomic ratio of around 4:2:3.

In the case of using an In-M-Zn oxide as the semiconductor 663, when thesummation of In and M is assumed to be 100 atomic %, the proportions ofIn and M are preferably set to be less than 50 atomic % and greater than50 atomic %, respectively, more preferably less than 25 atomic % andgreater than 75 atomic %, respectively. Note that the semiconductor 663and the semiconductor 661 may be formed using the same type of oxide.Note that the semiconductor 661 and/or the semiconductor 663 do/does notnecessarily contain indium in some cases. For example, the semiconductor661 and/or the semiconductor 663 may be gallium oxide.

Next, a function and an effect of the semiconductor 660 in which thesemiconductor 661, the semiconductor 662, and the semiconductor 663 arestacked will be described using an energy band diagram in FIG. 10B. FIG.10A is an enlarged view of the channel portion of the transistor 600illustrated in FIG. 9B. FIG. 10B shows an energy band diagram of aportion along chain line A1-A2 in FIG. 10A. In other words, FIG. 10Billustrates the energy band diagram of a channel formation region of thetransistor 600.

In FIG. 10B, Ec652, Ec661, Ec662, Ec663, and Ec653 indicate the energyof the conduction band minimum of the insulating film 652, thesemiconductor 661, the semiconductor 662, the semiconductor 663, and theinsulating film 653, respectively.

Here, a difference in energy between the vacuum level and the conductionband minimum (the difference is also referred to as electron affinity)corresponds to a value obtained by subtracting an energy gap from adifference in energy between the vacuum level and the valence bandmaximum (the difference is also referred to as ionization potential).The energy gap can be measured using a spectroscopic ellipsometer. Theenergy difference between the vacuum level and the valence band maximumcan be measured using an ultraviolet photoelectron spectroscopy (UPS)device.

Since the insulating film 652 and the insulating film 653 areinsulators, Ec652 and Ec653 are closer to the vacuum level than Ec661,Ec662, and Ec663. That is, the insulating film 652 and the insulatingfilm 653 have a smaller electron affinity than the semiconductor 661,the semiconductor 662, and the semiconductor 663.

As the semiconductor 662, an oxide having an electron affinity higherthan those of the semiconductors 661 and 663 is used. For example, asthe semiconductor 662, an oxide having an electron affinity higher thanthose of the semiconductors 661 and 663 by 0.07 eV or higher and 1.3 eVor lower, preferably 0.1 eV or higher and 0.7 eV or lower, morepreferably 0.15 eV or higher and 0.4 eV or lower is used. Note that theelectron affinity refers to an energy difference between the vacuumlevel and the conduction band minimum.

An indium gallium oxide has a small electron affinity and a highoxygen-blocking property. Therefore, the semiconductor 663 preferablyincludes an indium gallium oxide. The gallium atomic ratio [Ga/(In +Ga)]is, for example, higher than or equal to 70%, preferably higher than orequal to 80%, more preferably higher titan or equal to 90%.

At this time, when a gate voltage is applied, a channel is formed in thesemiconductor 662 having the highest electron affinity among thesemiconductors 661 to 663.

Here, in some cases, there is a mixed region of the semiconductor 661and the semiconductor 662 between the semiconductor 661 and thesemiconductor 662. Furthermore, in some cases, there is a mixed regionof the semiconductor 662 and the semiconductor 663 between thesemiconductor 662 and the semiconductor 663. The mixed region has a lowinterface state density. For that reason, the stack of the semiconductor661, the semiconductor 662, and the semiconductor 663 has a bandstructure where energy at each interface and in the vicinity of theinterface is changed continuously (also referred to as a band structurewith a continuous junction).

At this time, electrons move mainly in the semiconductor 662, not in thesemiconductor 661 and the semiconductor 663. As described above, whenthe interface state density at the interface between the semiconductor661 and the semiconductor 662 and the interface state density at theinterface between the semiconductor 662 and the semiconductor 663 aredecreased, electron movement in the semiconductor 662 is less likely tobe inhibited and the on-sate current of the transistor can be increased.

As factors of inhibiting electron movement are decreased, the on-statecurrent of the transistor can be increased. For example, in the casewhere there is no factor of inhibiting electron movement, electrons areassumed to be efficiently moved. Electron movement is inhibited, forexample, in the case where physical unevenness in a channel formationregion is large.

To increase the on-state current of the transistor, for example, rootmean square (RMS) roughness with a measurement area of 1 μm×1 μm of atop surface or a bottom surface of the semiconductor 662 (a formationsurface; here, the semiconductor 661) is less than 1 nm, preferably lessthan 0.6 nm, more preferably less than 0.5 nm, still more preferablyless than 0.4 nm. The average surface roughness (also referred to as Ra)with the measurement area of 1 μm×1 μm is less than 1 nm, preferablyless than 0.6 nm, more preferably less than 0.5 nm, still morepreferably less than 0.4 nm. The maximum difference (P-V) with themeasurement area of 1 μm×1 μm is less titan 10 nm, preferably less than9 nm, more preferably less than 8 nm, still more preferably less than 7nm. Note that RMS roughness, Ra, and P-V can be measured using ascanning probe microscope SPA-500 manufactured by SII Nano TechnologyInc.

The electron movement is also inhibited, for example, in the case wherethe density of defect states is high in a region where a channel isformed.

For example, in the case where the semiconductor 662 contains oxygenvacancies (also denoted by V_(O)), donor levels are formed by entry ofhydrogen into sites of oxygen vacancies in some cases. A state in whichhydrogen enters sites of oxygen vacancies is denoted by V_(O)H in thefollowing description in some cases. V_(O)H is a factor of decreasingthe on-slate current of the transistor because V_(O)H scatterselectrons. Note that sites of oxygen vacancies become more stable byentry of oxygen than by entry of hydrogen. Thus, by decreasing oxygenvacancies in the semiconductor 662, the on-state current of thetransistor can be increased in some cases.

For example, the hydrogen concentration at a certain depth in thesemiconductor 662 or in a certain region of the semiconductor 662, whichis measured by secondary ion mass spectrometry (SIMS), is higher than orequal to 1×10¹⁶ atoms/cm³ and lower than or equal to 2×10²⁰ atoms/cm³,preferably higher than or equal to 1×10¹⁶ atoms/cm³ and lower than orequal to 5×10¹⁹ atoms/cm³, further preferably higher than or equal to1×10¹⁶ atoms/cm³ and lower than or equal to 1×10¹⁹ atoms/cm³, and stillfurther preferably higher than or equal to 1×10¹⁶ atoms/cm³ and lowerthan or equal to 5×10¹⁸ atoms/cm³.

To decrease oxygen vacancies in the semiconductor 662, for example,there is a method in which excess oxygen in the insulating film 652 ismoved to the semiconductor 662 through the semiconductor 661. In thiscase, the semiconductor 661 is preferably a layer having oxygenpermeability (a layer through which oxygen can permeate).

In the case where the transistor has an s-channel structure, a channelis formed in the whole of the semiconductor 662. Therefore, as thesemiconductor 662 has a larger thickness, a channel region becomeslarger. In other words, the thicker the semiconductor 662 is, the higherthe on-state current of the transistor is.

Moreover, the thickness of the semiconductor 663 is preferably as smallas possible to increase the on-state current of the transistor. Forexample, the semiconductor 663 has a region with a thickness of lessthan 10 nm, preferably less than or equal to 5 nm, more preferably lessthan or equal to 3 nm. Meanwhile, the semiconductor 663 has a functionof blocking entry of elements other than oxygen (such as hydrogen andsilicon) included in the adjacent insulator into the semiconductor 662where a channel is formed. For this reason, it is preferable that thesemiconductor 663 have a certain thickness. For example, thesemiconductor 663 has a region with a thickness of greater than or equalto 0.3 nm, preferably greater than or equal to 1 nm, more preferablygreater than or equal to 2 nm. The semiconductor 663 preferably has anoxygen blocking property to suppress outward diffusion of oxygenreleased from the insulating film 652 and the like.

To improve reliability, preferably, the thickness of the semiconductor661 is large and the thickness of the semiconductor 663 is small. Forexample, the semiconductor 661 has a region with a thickness of greaterthan or equal to 10 nm, preferably greater than or equal to 20 nm, morepreferably greater than or equal to 40 nm, still more preferably greaterthan or equal to 60 nm. When the thickness of the semiconductor 661 ismade large, the distance from an interface between the adjacentinsulator and the semiconductor 661 to the semiconductor 662 in which achannel is formed can be large. However, to prevent the productivity ofthe semiconductor device from being decreased, the semiconductor 661 hasa region with a thickness of, for example, less than or equal to 200 nm,preferably less than or equal to 120 nm, more preferably less than orequal to 80 nm.

For example, a region with a silicon concentration of higher than orequal to 1×10¹⁶ atoms/cm³ and lower than 1×10¹⁹ atoms/cm³, preferablyhigher than or equal to 1×10¹⁶ atoms/cm³ and lower than 5×10¹⁸atoms/cm³, and further preferably higher than or equal to 1×10¹⁶atoms/cm³ and lower than 2×10¹⁸ atoms/cm³ which is measured by SIMSanalysis is provided between the semiconductor 662 and the semiconductor661. A region with a silicon concentration of higher than or equal to1×10¹⁶ atoms/cm³ and lower than 1×10¹⁹ atoms/cm³, preferably higher thanor equal to 1×10¹⁶ atoms/cm³ and lower than 5×10¹⁸ atoms/cm³, andfurther preferably higher than or equal to 1×10¹⁶ atoms/cm³ and lowerthan 2×10¹⁸ atoms/cm³ which is measured by SIMS is provided between thesemiconductor 662 and the semiconductor 663.

It is preferable to reduce the concentration, of hydrogen in thesemiconductor 661 and the semiconductor 663 in order to reduce theconcentration of hydrogen in the semiconductor 662. The semiconductor661 and the semiconductor 663 each have a region in which theconcentration of hydrogen measured by SIMS is higher than or equal to1×10¹⁶ atoms/cm³ and lower than or equal to 2×10²⁰ atoms/cm³, preferablyhigher than or equal to 1×10¹⁶ atoms/cm³ and lower than or equal to5×10¹⁹ atoms/cm³, further preferably higher than or equal to 1×10¹⁶atoms/cm³ and lower than or equal to 1×10¹⁹ atoms/cm³, and still furtherpreferably higher than or equal to 1×10¹⁶ atoms/cm³ and lower than orequal to 5×10¹⁸ atoms/cm³. It is preferable to reduce the concentrationof nitrogen in the semiconductor 661 and the semiconductor 663 in orderto reduce the concentration of nitrogen in the semiconductor 662. Thesemiconductor 661 and the semiconductor 663 each have a region in whichthe concentration of nitrogen measured by SIMS is higher than or equalto 1×10¹⁶ atoms/cm³ and lower than 5×10¹⁹ atoms/cm³, preferably higherthan or equal to 1×10¹⁶ atoms/cm³ and lower than or equal to 5×10¹⁸atoms/cm³, further preferably higher than or equal to 1×10¹⁶ atoms/cm³and lower than or equal to 1×10¹⁸ atoms/cm³, and still furtherpreferably higher than or equal to 1×10¹⁶ atoms/cm³ and lower than orequal to 5×10¹⁷ atoms/cm³.

The above three-layer structure is an example. For example, a two-layerstructure without the semiconductor 661 or the semiconductor 663 may beemployed. A four-layer structure in which any one of the semiconductorsdescribed as examples of the semiconductor 661, the semiconductor 662,and the semiconductor 663 is provided under or over the semiconductor661 or under or over the semiconductor 663 may be employed. An n-layerstructure (n is an integer of 5 or more) in which any one of thesemiconductors described as examples of the semiconductor 661, thesemiconductor 662, and the semiconductor 663 is provided at two or moreof the following positions: over the semiconductor 661, under thesemiconductor 661, over the semiconductor 663, and under thesemiconductor 663.

<<Method for Manufacturing Transistor>>

A method for manufacturing the transistor 600 illustrated in FIGS. 9A to9D will be described below with reference to FIGS. 11A to 11E and FIGS.12A to 12D. Note that cross-sectional views of the transistor in thechannel length direction (cross-sectional views along dashed-dotted lineY1-Y2 in FIG. 9A) are shown on the left side of FIGS. 11A to 11E andFIGS. 12A to 12D, and cross-sectional views of the transistor in thechannel width direction (cross-sectional views along dashed-dotted lineX1-X2 in FIG. 9A) are shown on the right side of FIGS. 11A to 11E andFIGS. 12A to 12D.

First, an insulating film 651 a is formed over the substrate 640. Then,the conductive film 674 is formed, followed by an insulating film 651 b(FIG. 11A).

As the substrate 640, for example, an insulator substrate, asemiconductor substrate, or a conductor substrate may be used. As theinsulator substrate, for example, a glass substrate, a quartz substrate,a sapphire substrate, a stabilized zirconia substrate (e.g., anyttria-stabilized zirconia substrate), or a resin substrate is used. Asthe semiconductor substrate, for example, a single materialsemiconductor substrate made of silicon, germanium, or the like; acompound semiconductor substrate made of silicon carbide, silicongermanium, gallium arsenide, indium phosphide, zinc oxide, or galliumoxide; or the like is used. A semiconductor substrate in which aninsulator region is provided in the above semiconductor substrate, e.g.,a silicon on insulator (SOI) substrate may also be used. As theconductor substrate, a graphite substrate, a metal substrate, an alloysubstrate, a conductive resin substrate, or the like is used. Asubstrate including a metal nitride, a substrate including a metaloxide, or the like is used. An insulator substrate provided with aconductor or a semiconductor, a semiconductor substrate provided with aconductor or an insulator, a conductor substrate provided with asemiconductor or an insulator, or the like may also be used.Alternatively, any of these substrates over which an element is providedmay be used. As the element provided over the substrate, a capacitor, aresistor, a switching element, a light-emitting element, a memoryelement, or the like is used.

Alternatively, a flexible substrate may be used as the substrate 640. Asa method for providing a transistor over a flexible substrate, there isa method in which the transistor is formed over a non-flexible substrateand then the transistor is separated and transferred to the substrate640 which is a flexible substrate. In that case, a separation layer ispreferably provided between the non-flexible substrate and thetransistor. As the substrate 640, a sheet, a film, or a foil containinga fiber may be used. The substrate 640 may have elasticity. Thesubstrate 640 may have a property of returning to its original shapewhen bending or pulling is stopped. Alternatively, the substrate 640 mayhave a property of not returning to its original shape. The thickness ofthe substrate 640 is, for example, greater than or equal to 5 μm andless than or equal to 700 μm, preferably greater than or equal to 10 μmand less than or equal to 500 μm, more preferably greater than or equalto 13 μm and less than or equal to 300 μm. When the substrate 640 has asmall thickness, the weight of the semiconductor device can be reduced.When the substrate 640 has a small thickness, even in the case of usingglass or the like, the substrate 640 may have elasticity or a propertyof returning to its original shape when bending or pulling is stopped.Therefore, an impact applied to the semiconductor device over thesubstrate 640, which is caused by dropping or the like, can be reduced.That is, a durable semiconductor device can be provided.

For the substrate 640 which is a flexible substrate, for example, metal,an alloy, resin, glass, or fiber thereof can be used. The flexiblesubstrate 640 preferably has a lower coefficient of linear expansionbecause deformation due to an environment is suppressed. The flexiblesubstrate 640 is formed using, for example, a material whose coefficientof linear expansion is lower than or equal to 1×10⁻³/K, lower than orequal to 5×10⁻⁵/K, or lower than or equal to 1×10⁻⁵/K. Examples of theresin include polyester, polyolefin, polyamide (e.g., nylon or aramid),polyimide, polycarbonate, acrylic, and polytetrafluoroethylene (FIFE).In particular, aramid is preferably used for the flexible substrate 640because of its low coefficient of linear expansion.

As a material for the insulating films 651 a and 651 b, a materialcontaining silicon oxide, silicon nitride, silicon oxynitride, orsilicon nitride oxide is preferably used. Alternatively, a metal oxidesuch as aluminum oxide, aluminum oxynitride, gallium oxide, galliumoxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, or hafniumoxynitride can be used. Note that in this specification, “oxynitride”refers to a material that contains oxygen at a higher proportion thannitrogen, and a “nitride oxide” refers to a material that containsnitrogen at a higher proportion than oxygen.

The insulating films 651 a and 651 b may be formed using silicon oxidewith high step coverage which is formed by reacting tetraethylorthosilicate (TEOS), silane, or the like with oxygen, nitrous oxide, orthe like.

The insulating films 651 a and 651 b may be formed by a sputteringmethod, a chemical vapor deposition (CVD) method (including a thermalCVD method, a metal organic CVD (MOCVD) method, a plasma enhanced CVD(PECVD) method, and the like), a molecular beam epitaxy (MBE) method, anatomic layer deposition (ALD) method, a pulsed laser deposition (PCD)method, or the like. In particular, it is preferable that the insulatingfilms be formed by a CVD method and further preferably a plasma CVDmethod, because coverage can be further improved. It is preferable touse a thermal CVD method, an MOCVD method, or an ALD method in order toreduce plasma damage.

In the case of using a semiconductor substrate as the substrate 640, theinsulating film 651 a may be formed using a thermal oxide film.

The conductive film 674 preferably has a single-layer structure or astacked-layer structure of a conductive film containing a low-resistancematerial selected from copper (Cu), tungsten (W), molybdenum (Mo), gold(Au), aluminum (Al), manganese (Mn), titanium fit), tantalum (Ta),nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co),ruthenium (Ru), platinum (Pt), iridium (Ir), and strontium (Sr), analloy of such a low-resistance material, or a compound containing such amaterial as its main component. It is particularly preferable to use ahigh-melting-point material which has both heat resistance andconductivity, such as tungsten or molybdenum. In addition, theconductive films are preferably formed using a low-resistance conductivematerial such as aluminum or copper. The conductive films are furtherpreferably formed using a Cu—Mn alloy, in which case manganese oxideformed at the interface with an insulator containing oxygen has afunction of preventing Cu diffusion.

The conductive film 674 can be formed by a sputtering method, a CVDmethod (including a thermal CVD method, an MOCVD method, a PECVD method,and the like), an MBE method, an ALD method, a PLD method, or the like.

Next, a surface of the insulating film 651 b is subjected toplanarization by a chemical mechanical polishing (CMP) method (sec FIG.11B).

As the insulating film 651 b, a planarization film may be used. At thistime, a CMP method or the like is not necessarily used forplanarization. The planarization film can be formed by, for example, anatmospheric pressure CVD method, a coating method, or the like. Anexample of a film which can be formed by an atmospheric pressure CVDmethod is a film of boron phosphorus silicate glass (BPSG). Furthermore,an example of a film which can be formed by a coating method is a filmof hydrogen silsesquioxane (HSQ).

Hereinafter, the insulating films 651 a and 651 b are collectivelyreferred to as the insulating film 651.

Next, the insulating film 656, the insulating film 652, a semiconductor661 i, and a semiconductor 662 i are formed (see FIG. 11C).

The insulating films 656 and 652 may be formed by a sputtering method, aCVD method (including a thermal CVD method, an MOCVD method, a PECVDmethod, and the like), an MBE method, an ALD method, a PLD method, orthe like.

The insulating film 656 preferably has a blocking effect against oxygen,hydrogen, water, alkali metal, alkaline earth metal, and the like. Theinsulating film 656 can be, for example, a nitride insulating film. Thenitride insulating film is formed using silicon nitride, silicon nitrideoxide, aluminum nitride, aluminum nitride oxide, or the like. Note thatinstead of the nitride insulating film, an oxide insulating film havinga blocking effect against oxygen, hydrogen, water, and the like, may beprovided. As the above oxide insulating film, an aluminum oxide film, analuminum oxynitride film, a gallium oxide film, a gallium oxynitridefilm, an yttrium oxide film, an yttrium oxynitride film, a hafnium oxidefilm, and a hafnium oxynitride film can be given.

The insulating film 652 preferably contains an oxide that can supplyoxygen to the semiconductor 660. For example, for the insulating film652, a material containing silicon oxide or silicon oxynitride ispreferably used. Alternatively, a metal oxide such as aluminum oxide,aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide,yttrium oxynitride, hafnium oxide, or hafnium oxynitride can be used.

To make the insulating film 652 contain excess oxygen, the insulatingfilm 652 may be formed in an oxygen atmosphere, for example.Alternatively, a region containing excess oxygen may be formed byintroducing oxygen into the insulating film 652 that has been formed.Both the methods may be combined.

For example, oxygen (at least including any of oxygen radicals, oxygenatoms, and oxygen ions) is introduced into the insulating film 652 whichhas been formed, whereby a region containing excess oxygen is formed.Oxygen can be introduced by an ion implantation method, an ion dopingmethod, a plasma immersion ion implantation method, plasma treatment, orthe like.

A gas containing oxygen can be used for oxygen introducing treatment. Asthe gas containing oxygen, oxygen, nitrous oxide, nitrogen dioxide,carbon dioxide, carbon monoxide, and the like can be used. Furthermore,a rare gas may be included in the gas containing oxygen for the oxygenintroduction treatment. Moreover, hydrogen or the like may be included.

After the insulating film 652 is formed, the insulating film 652 may besubjected to planarization treatment using a CMP method or the like toimprove the planarity the top surface thereof.

The semiconductors 661 i and 662 i are preferably formed successivelywithout contact with the air. The semiconductors 661 i and 662 i areformed by a sputtering method, a CVD method (including a thermal CVDmethod, an MOCVD method, a PECVD method, and the like), an MBE method, aPLD method, an ALD method, or the like.

The description of the semiconductors 661 and 662 in FIGS. 9A to 9D canbe referred to for a material that can be used for the semiconductors661 i and 662 i.

Note that in the case where In—Ga—Zn oxide layers formed by an MOCVDmethod are used as the semiconductors 661 i and 662 i, trimethylindium,trimethylgallium, dimethylzinc, and the like may be used as sourcegases. The source gases are not limited to the above combination, andtriethylindium or the like may be used instead of trimethylindium.Alternatively, triethylgallium or the like may be used instead oftrimethylgallium. Further alternatively, diethylzinc or the like may beused instead of dimethylzinc.

Here, after the semiconductor 661 i is formed, oxygen may be introducedinto the semiconductor 661 i. For example, oxygen (at least includingany of oxygen radicals, oxygen atoms, and oxygen ions) is introducedinto the semiconductor 661 i which has been formed, whereby a regioncontaining excess oxygen is formed. Oxygen can be introduced by an ionimplantation method, an ion doping method, a plasma immersion ionimplantation method, plasma treatment, or the like.

A gas containing oxygen can be used for oxygen introducing treatment. Asthe gas containing oxygen, oxygen, nitrous oxide, nitrogen dioxide,carbon dioxide, carbon monoxide, and the like can be used. Furthermore,a rare gas may be included in the gas containing oxygen for the oxygenintroduction treatment. Moreover, hydrogen or the like may be included.

After the semiconductors 661 i and 662 i are formed, heat treatment ispreferably performed. The heat treatment may be performed at atemperature higher than or equal to 250° C. and lower than or equal to650° C., preferably higher than or equal to 300° C. and lower than orequal to 500° C., in an inert gas atmosphere, an atmosphere containingan oxidizing gas at 10 ppm or more, or a reduced pressure state.Alternatively, the heat treatment may be performed in such a manner thatheat treatment is performed in an inert gas atmosphere, and then anotherheat treatment is performed in an atmosphere containing an oxidizing gasat 10 ppm or more, in order to compensate for released oxygen. The heattreatment may be performed directly after the formation of oxidesemiconductor films or may be performed after the oxide semiconductorfilms are processed into the island-shaped semiconductors 661 and 662.Through the heat treatment, oxygen can be supplied to the semiconductorsfrom the insulating film 652 and the oxide film; thus, oxygen vacanciesin the semiconductors can be reduced.

Then, a resist mask is formed by a method similar to that describedabove, and an unnecessary portion is removed by etching. Then, theresist mask is removed. In this manner, a stacked-layer structureincluding the Island-shaped semiconductors 661 and 662 can be formed(see FIG. 11D). Note that, in some cases, part of the insulating film652 is etched in the etching of the semiconductor films to reduce thethickness of a portion of the insulating film 652 which is not coveredwith the semiconductors 661 and 662. For this reason, the insulatingfilm 652 is preferably formed to have a large thickness so as not to beremoved by the etching.

Note that there is a possibility that the resist is totally removeddepending on the etching conditions of the semiconductor films;therefore, what is called a hard mask formed of a material with highresistance to etching, such as an inorganic film or a metal film, may beused. Here, for example, a conductive film is used as a hard mask 678,and the semiconductor film is processed using the hard mask 678 to formthe semiconductors 661 and 662 (see FIG. 11E).

The hard mask 678 preferably has a single-layer structure or astacked-layer structure of a conductive film containing a low-resistancematerial selected from copper (Cu), tungsten (W), molybdenum (Mo), gold(Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta),nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fc), cobalt (Co),ruthenium (Ru), platinum (Pt), iridium (Ir), and strontium (Sr), analloy of such a low-resistance material, or a compound containing such amaterial as its main component. It is particularly preferable to use ahigh-melting-point material which has both heat resistance andconductivity, such as tungsten or molybdenum. In addition, theconductive films are preferably formed using a low-resistance conductivematerial such as aluminum or copper. The conductive films are furtherpreferably formed using a Cu—Mn alloy, in which case manganese oxideformed at the interface with an insulator containing oxygen has afunction of preventing Cu diffusion.

The hand mask 678 is preferably formed using a conductive oxideincluding noble metal, such as iridium oxide, ruthenium oxide, orstrontium ruthenate. Such a conductive oxide hardly takes oxygen from anoxide semiconductor even when it is in contact with the oxidesemiconductor and hardly generates oxygen vacancies in the oxidesemiconductor.

The hard mask 678 can be formed by a sputtering method, a CVD method(including a thermal CVD method, an MOCVD method, a PECVD method, andthe like), an MBE method, an ALD method, a PLD method, or the like.

Next, a resist mask is formed, and the hard mask 678 is processed intothe conductive films 671 and 672 by etching (see FIG. 12A). Note that insome cases, upper portions of the semiconductor 662 and the insulatingfilm 652 are partly etched in etching of the hard mask 678, so that aportion not overlapping with the conductive film 671 or 672 is thinned.For this reason, the semiconductor 662 is preferably formed to have alarge thickness in advance in consideration of the etching depth.

Then, the semiconductor 663 and the insulating film 653 are formed.After that, a resist mask is formed, the semiconductor 663 and theinsulating film 653 are processed by etching, and the resist mask isremoved (sec FIG. 12B).

Next, the conductive film 673 is deposited, a resist mask is formed, theconductive film 673 is processed by etching, and the resist mask isremoved, whereby a gate electrode is formed (see FIG. 12C).

The semiconductor 663, the insulating film 653, and the conductive film673 may be formed by a sputtering method, a CVD method (including athermal CVD method, an MOCVD method, a PECVD method, and the like), anMBE method, a PLD method, an ALD method, or the like. In particular, itis preferable to use a CVD method and further preferably a plasma CVDmethod, because coverage can be further improved, ft is preferable touse a thermal CVD method, an MOCVD method, or an ALD method in order toreduce plasma damage.

The semiconductor 663 and the insulating film 653 may be etched afterthe conductive film 673 is formed. The etching may be performed with aresist mask, for example. Alternatively, the insulating film 653 and thesemiconductor 663 may be etched using the conductive film 673 as a mask.

After the semiconductor 663 is formed, oxygen may be introduced into thesemiconductor 663. For example, oxygen (at least including any of oxygenradicals, oxygen atoms, and oxygen ions) is introduced into thesemiconductor 663 which has been formed, whereby a region containingexcess oxygen is formed. Oxygen can be introduced by an ion implantationmethod, an ion doping method, a plasma immersion ion implantationmethod, plasma treatment, or the like.

A gas containing oxygen can be used for oxygen introducing treatment. Asthe gas containing oxygen, oxygen, nitrous oxide, nitrogen dioxide,carbon dioxide, carbon monoxide, and the like can be used. Furthermore,a rare gas may be included in the gas containing oxygen for (lie oxygenintroduction treatment. Moreover, hydrogen or the like may be included.

The description of the semiconductor 663 in FIGS. 9A to 9D can bereferred to for a material that can be used for the semiconductor 663.

The insulating film 653 can be formed using an insulating filmcontaining at least one of aluminum oxide, magnesium oxide, siliconoxide, silicon oxynitride, silicon nitride oxide, silicon nitride,gallium oxide, germanium oxide, yttrium oxide, zirconium oxide,lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Theinsulating film 653 may be a stack including any of the above materials.The insulating film 653 may contain lanthanum (La), nitrogen, orzirconium (Zr) as an impurity.

An example of a stacked-layer structure of the insulating film 653 isdescribed. The insulating film 653 contains oxygen, nitrogen, silicon,or hafnium, for example. Specifically, the insulating film 653preferably includes hafnium oxide and silicon oxide or siliconoxynitride.

Hafnium oxide has a higher dielectric constant than silicon oxide andsilicon oxynitride. Therefore, the thickness of the insulating film 653can be made large as compared with the case where silicon oxide is used;as a result, a leakage current due to a tunnel current can be low. Thatis, it is possible to provide a transistor with a low off-state current.

Next, the insulating film 654 is formed. The insulating film 654 has ablocking effect against oxygen, hydrogen, water, alkali metal, alkalineearth metal, and the like. The insulating film 654 can be formed by asputtering method, a CVD method (including a thermal CVD method, anMOCVD method, a PECVD method, and the like), an MBE method, an ALDmethod, a PLD method, or the like, for example. In particular, it ispreferable that the insulating film be formed by a CVD method andfurther preferably a plasma CVD method, because coverage can be furtherimproved. It is preferable to use a thermal CVD method, an MOCVD method,or an ALD method in order to reduce plasma damage.

The insulating film 654 preferably has a blocking effect against oxygen,hydrogen, water, alkali metal, alkaline earth metal, and the like. Theinsulating film 654 can be, for example, a nitride insulating film. Thenitride insulating film is formed using silicon nitride, silicon nitrideoxide, aluminum nitride, aluminum nitride oxide, or the like. Note thatinstead of the nitride insulating film, an oxide insulating film havinga blocking effect against oxygen, hydrogen, water, and the like, may beprovided. As the oxide insulating film, an aluminum oxide film, analuminum oxynitride film, a gallium oxide film, a gallium oxynitridefilm, an yttrium oxide film, an yttrium oxynitride film, a hafnium oxidefilm, and a hafnium oxynitride film can be given.

An aluminum oxide film is preferably used as the insulating film 654because it is highly effective in preventing transmission of both oxygenand impurities such as hydrogen and moisture. In addition, oxygencontained in the aluminum oxide film can be diffused into thesemiconductor 660.

After the insulating film 654 is formed, heat treatment is preferablyperformed. Through this heat treatment, oxygen can be supplied to thesemiconductor 660 from the insulating film 652 or the like; thus, oxygenvacancies in the semiconductor 660 can be reduced. Because oxygenreleased from the insulating film 652 is blocked by the insulating film656 and the insulating film 654 at this time, the oxygen can beeffectively confined. Thus, the amount of oxygen supplied to thesemiconductor 660 can be increased, so that oxygen vacancies in thesemiconductor 660 can be effectively reduced.

Next, the insulating film 655 is formed. The insulating film 655 can beformed by a sputtering method, a CVD method (including a thermal CVDmethod, an MOCVD method, a PECVD method, and the like), an MBE method,an ALD method, a PLD method, or the like. In particular, it ispreferable that the insulating film be formed by a CVD method andfurther preferably a plasma CVD method, because coverage can beimproved. It is preferable to use a thermal CVD method, an MOCVD method,or an ALD method in order to reduce plasma damage. In the case where theinsulating film 655 is formed using an organic insulating material suchas an organic resin, a coating method such as a spin coating method maybe used. After the insulating film 655 is formed, a top surface thereofis preferably subjected to planarization treatment.

The insulating film 655 can be formed using an insulator containing atleast one of aluminum oxide, aluminum nitride oxide, magnesium oxide,silicon oxide, silicon oxynitride, silicon nitride oxide, siliconnitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide,lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and thelike. Alternatively, for the insulating film 655, an organic resin suchas a polyimide resin, a polyamide resin, an acrylic resin, a siloxaneresin, an epoxy resin, or a phenol resin can be used. The insulatingfilm 655 may be a stack including any of the above materials.

<<Structure Example 2 of Transistor>>

In the transistor 600 illustrated in FIGS. 9A to 9D, the semiconductor663 and the insulating film 653 may be etched at the same time when theconductive film 673 is formed by etching. FIG. 13 illustrates an exampleof such a case.

FIG. 13 illustrates the case where the semiconductor 663 and theinsulating film 653 in FIG. 9B are provided only under the conductivefilm 673.

<<Structure Example 3 of Transistor>>

In the transistor 600 illustrated in FIGS. 9A to 9D, the conductivefilms 671 and 672 may be in contact with side surfaces of thesemiconductors 661 and 662. FIG. 14 illustrates an example of such acase.

FIG. 14 illustrates the case where the conductive films 671 and 672 inFIG. 9B are in contact with the side surfaces of the semiconductors 661and 662.

<<Structure Example 4 of Transistor>>

In the transistor 600 illustrated in FIGS. 9A to 9D, the conductive film671 may be a stack including a conductive film 671 a and a conductivefilm 671 b. Furthermore, the conductive film 672 may be a stackincluding a conductive film 672 a and a conductive film 672 b. FIG. 15illustrates an example of such a case.

FIG. 15 illustrates the case where the conductive film 671 and theconductive film 672 in FIG. 9B are a stack including the conductivefilms 671 a and 671 b and a stack including the conductive films 672 aand 672 b, respectively.

The conductive films 671 b and 672 b may be formed using a transparentconductor, an oxide semiconductor, a nitride semiconductor, or anoxynitride semiconductor, for example. The conductive films 671 b and672 b may be formed using, for example, a film containing indium, tin,and oxygen, a film containing indium and zinc, a film containing indium,tungsten, and zinc, a film containing tin and zinc, a film containingzinc and gallium, a film containing zinc and aluminum, a film containingzinc and fluorine, a film containing zinc and boron, a film containingtin and antimony, a film containing tin and fluorine, a film containingtitanium and niobium, or the like. Alternatively, any of these films maycontain hydrogen, carbon, nitrogen, silicon, germanium, or argon.

The conductive films 671 b and 672 b may have a property of transmittingvisible light. Alternatively, the conductive films 671 b and 672 b mayhave a property of not transmitting visible light, ultraviolet light,infrared light, or X-rays by reflecting or absorbing it. In some cases,such a property can suppress a change in electrical characteristics ofthe transistor due to stray light.

The conductive films 671 b and 672 b may preferably be formed using alayer which does not form a Schottky barrier with the semiconductor 662or the like. Accordingly, on-state characteristics of the transistor canbe improved.

Each of the conductive films 671 a and 672 a may be formed to have, forexample, a single-layer structure or a stacked-layer structure includinga conductor containing one or more kinds of boron, nitrogen, oxygen,fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese,cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum,ruthenium, silver, indium, tin, tantalum, and tungsten. For example, analloy film or a compound film may be used, and a conductor containingaluminum, a conductor containing copper and titanium, a conductorcontaining copper and manganese, a conductor containing indium, tin, andoxygen, a conductor containing titanium and nitrogen, or the like may beused.

Note dial the conductive films 671 b and 672 b may preferably be formedusing a film having a resistance higher than that of the conductivefilms 671 a and 672 a. The conductive films 671 b and 672 b maypreferably be formed using a film having a resistance lower than that ofthe channel of the transistor. For example, the conductive films 671 band 672 b may have a resistivity higher than or equal to 0.1 Ωcm andlower than or equal to 100 Ωcm, higher than or equal to 0.5 Ωcm andlower than or equal to 50 Ωcm, or higher than or equal to 1 Ωcm andlower than or equal to 10 Ωcm. The conductive films 671 b and 672 bhaving a resistivity within the above range can reduce electric fieldconcentration in a boundary portion between the channel and the drain.Therefore, a change in electrical characteristics of the transistor canbe suppressed. In addition, a punch-through current generated by anelectric field from the drain can be reduced. Thus, a transistor with asmall channel length can have favorable saturation characteristics. Notethat in a circuit configuration where the source and the drain do notinterchange, only one of the conductive films 671 b and 672 b (e.g., thefilm on the drain side) may preferably be provided.

<<Structure Example 5 of Transistor>>

FIGS. 16A and 16B are a top view and a cross-sectional view of atransistor 300. FIG. 16A is the top view. FIG. 16B illustrates a crosssection along dashed-dotted line A-B in FIG. 16A. In FIGS. 16A and 16B,some components are scaled up or down or omitted for easy understanding.The direction of the dashed-dotted line A-B can be referred to as achannel length direction.

The transistor 300 illustrated in FIG. 16B includes a conductive film380 serving as a first gate, a conductive film 388 serving as a secondgate, a semiconductor 382, a conductive film 383 and a conductive film384 serving as a source and a drain, an insulating film 381, aninsulating film 385, an insulating film 386, and an insulating film 387.

The conductive film 380 is on an insulating surface. The conductive film380 overlaps with the semiconductor 382 with the insulating film 381provided therebetween. The conductive film 388 overlaps with thesemiconductor 382 with the insulating films 385, 386, and 387 providedtherebetween. The conductive films 383 and 384 are connected to thesemiconductor 382.

The descriptions of the conductive films 673 and 674 in FIGS. 9A to 9Dcan be referred to for the details of the conductive films 380 and 388.

The conductive films 380 and 388 may be supplied with differentpotentials, or may be supplied with the same potential at the same time.The conductive film 388 serving as a second gate electrode in thetransistor 300 leads to stabilization of threshold voltage. Note thatthe conductive film 388 is unnecessary in some cases.

The description of the semiconductor 662 in FIGS. 9A to 9D can bereferred to for the details of the semiconductor 382. The semiconductor382 may be a single layer or a stack including a plurality ofsemiconductor layers.

The descriptions of the conductive films 671 and 672 in FIGS. 9A to 9Dcan be referred to for the details of the conductive films 383 and 384.

The description of the insulating film 653 in FIGS. 9A to 9D can bereferred to for the details of the insulating film 381.

The insulating films 385 to 387 are sequentially stacked over thesemiconductor 382 and the conductive films 383 and 384 in FIG. 16B;however, an insulating film provided over the semiconductor 382 and theconductive films 383 and 384 may be a single layer or a stack includinga plurality of insulating films.

In the case of using an oxide semiconductor as the semiconductor 382,the insulating film 386 preferably contains oxygen at a proportionhigher than or equal to the stoichiometric composition and has afunction of supplying part of oxygen to the semiconductor 382 byheating. Note that in the case where the semiconductor 382 is damaged atthe time of formation of the insulating film 386 when the insulatingfilm 386 is directly formed on the semiconductor 382, the insulatingfilm 385 is preferably provided between the semiconductor 382 and theinsulating film 386, as illustrated in FIG. 16B. The insulating film 385preferably causes little damage to foe semiconductor 382 when theinsulating film 385 is formed compared with the case of the insulatingfilm 386 and has a function of passing oxygen. If damage to thesemiconductor 382 can be reduced and the insulating film 386 can beformed directly on the semiconductor 382, the insulating film 385 is notnecessarily provided.

For the insulating films 386 and 385, a material containing siliconoxide or silicon oxynitride is preferably used, for example.Alternatively, a metal oxide such as aluminum oxide, aluminumoxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttriumoxynitride, hafnium oxide, or hafnium oxynitride can be used.

The insulating film 387 preferably has an effect of blocking diffusionof oxygen, hydrogen, and water. Alternatively, the insulating film 387preferably has an effect of blocking diffusion of hydrogen and water.

As an insulating film has higher density and becomes denser or has afewer dangling bonds and becomes more chemically stable, the insulatingfilm has a higher blocking effect. An insulating film that has an effectof blocking diffusion of oxygen, hydrogen, and water can be formedusing, for example, aluminum oxide, aluminum oxynitride, gallium oxide,gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, orhafnium oxynitride. An insulating film that has an effect of blockingdiffusion of hydrogen and water can be formed using, for example,silicon nitride or silicon nitride oxide.

In the case where the insulating film 387 has an effect of blockingdiffusion of water, hydrogen, and the like, impurities such as water andhydrogen that exist in a resin in a panel or exist outside the panel canbe prevented from entering the semiconductor 382. Since an oxidesemiconductor is used for the semiconductor 382, part of water orhydrogen entering the oxide semiconductor serves as an electron donor(donor). Thus, the use of the insulating film 387 having the blockingeffect can prevent a shift in threshold voltage of the transistor 300due to generation of donors.

In addition, since an oxide semiconductor is used for the semiconductor382, when the insulating film 387 has an effect of blocking diffusion ofoxygen, diffusion of oxygen from the oxide semiconductor to the outsidecan be prevented. Accordingly, oxygen vacancies in the oxidesemiconductor that serve as donors are reduced, so that a shift inthreshold voltage of the transistor 300 due to generation of donors canbe prevented.

The structures, methods, and the like described in this embodiment canbe used as appropriate in combination with any of the structures,methods, and the like described in other embodiments.

Embodiment 4

In this embodiment, examples of a memory device to which the transistorM0 described in Embodiments 1 and 2 can be applied will be described.

A semiconductor device illustrated in FIG. 17A includes the transistorM1, the transistor M0, and a capacitor 3400.

A channel region of the transistor M0 preferably contains an oxidesemiconductor. Since the off-state current of the transistor M0 is low,stored data can be retained for a long period. In other words, powerconsumption can be sufficiently reduced because a semiconductor memorydevice in which refresh operation is unnecessary or the frequency ofrefresh operation is extremely low can be provided.

In FIG. 17A, a first wiring 3001 is electrically connected to the sourceof the transistor M1. A second wiring 3002 is electrically connected tothe drain of the transistor M1. A third wiring 3003 is electricallyconnected to one of the source and the drain of the transistor M0. Afourth wiring 3004 is electrically connected to the gate of thetransistor M0. The gate of the transistor M1 and the other of the sourceand the drain of the transistor M0 are electrically connected to a firstterminal of the capacitor 3400. A fifth wiring 3005 is electricallyconnected to a second terminal of the capacitor 3400.

The semiconductor device in FIG. 17A has a feature that the potential ofthe gate of the transistor M1 can be retained, and thus enables writing,retaining, and reading of data as follows.

Writing and retaining of data are described. First, the potential of thefourth wiring 3004 is set to a potential at which the transistor M0 isturned on, so that the transistor M0 is turned on. Accordingly, thepotential of the third wiring 3003 is supplied to the gate of thetransistor M1 and the capacitor 3400. That is, a predetermined charge issupplied to the gate of the transistor M1 (writing). Here, one of twokinds of charges providing different potential levels (hereinafterreferred to as a low-level charge and a high-level charge) is supplied.After that, the potential of the fourth wiring 3004 is set to apotential at which the transistor M0 is turned off, so that thetransistor M0 is turned off. Thus, the charge supplied to the gate ofthe transistor M1 is held (retaining).

Since the off-state current of the transistor M0 is extremely low, thecharge of the gate of the transistor M1 is retained for a long time.

Next, reading of data is described. An appropriate potential (a readingpotential) is supplied to the fifth wiring 3005 while a predeterminedpotential (a constant potential) is supplied to the first wiring 3001,whereby the potential of the second wiring 3002 varies depending on theamount of charge retained in the gate of the transistor M1. Thus isbecause in the case of using an n-channel transistor as the transistorM1, an apparent threshold voltage V_(th_H) at the time when thehigh-level charge is given to the gate of the transistor M1 is lowerthan an apparent threshold voltage V_(th_L) at the time when thelow-level charge is given to the gate of the transistor M1. Here, anapparent threshold voltage refers to the potential of the fifth wiring3005 which is needed to turn on the transistor M1. Thus, the potentialof the fifth wiring 3005 is set to a potential V₀ which is betweenV_(th_H) and V_(th_L), whereby charge supplied to the gate of thetransistor M1 can be determined. For example, in the case where thehigh-level charge is supplied to the gate of the transistor M1 inwriting and the potential of the fifth wiring 3005 is V₀ (>V_(th_H)),the transistor M1 is turned on. In the case where the low-level chargeis supplied to the gate of the transistor M1 in writing, even when thepotential of the fifth wiring 3005 is V₀ (V_(th_L)), the transistor M1remains off. Thus, the data retained in the gate of the transistor M1can be read by determining the potential of the second wiring 3002.

Note dial in the case where memory cells are arrayed, it is necessarythat data of a desired memory cell be read. In the case where suchreading is not performed, the fifth wiring 3005 may be supplied with apotential at which the transistor M1 is turned off regardless of thestate of the gate, that is, a potential lower than V_(th_H).Alternatively, the fifth wiring 3005 may be supplied with a potential atwhich the transistor M1 is turned on regardless of the state of thegate, that is, a potential higher than V_(th_L).

The semiconductor device illustrated in FIG. 17B is different from thesemiconductor device illustrated in FIG. 17A in that the transistor M1is not provided. Also in this case, writing and retaining operation ofdata can be performed in a manner similar to the above.

Next, reading of data in the semiconductor device in FIG. 17B isdescribed. When the transistor M0 is turned on, the third wiring 3003which is in a floating state and the capacitor 3400 are electricallyconnected to each other, and the charge is redistributed between thethird wiring 3003 and the capacitor 3400. As a result, the potential ofthe third wiring 3003 is changed. The amount of change in potential ofthe third wiring 3003 varies depending on the potential of the firstterminal of the capacitor 3400 (or the charge accumulated in thecapacitor 3400).

For example, the potential of the third wiring 3003 after the chargeredistribution is (C_(B)×V_(B0)+C×V)/(C_(B)+C), where F is the potentialof the first terminal of the capacitor 3400, C is the capacitance of thecapacitor 3400, C_(B) is the capacitance component of the third wiring3003, and V_(B0) is the potential of the third wiring 3003 before thecharge redistribution. Thus, it can be found that, assuming that thememory cell is in either of two states in which the potential of thefirst terminal of the capacitor 3400 is V₁ and V₀ (V₁>V₀), the potentialof the third wiring 3003 in the case of retaining the potential V₁(=C_(B)−V_(B0)+C−V_(k))/(C_(B)+C)) is higher than the potential of thethird wiring 3003 in the case of retaining the potential V₀(=(C_(B)−V_(B0)+C×V₀)/(C_(B)+C)).

Then, by comparing the potential of the third wiring 3003 with apredetermined potential, data can be read.

When including a transistor in which a channel formation region isformed using an oxide semiconductor and which has an extremely towoff-state current, the semiconductor device described in this embodimentcan retain stored data for an extremely tong time. In other words, powerconsumption can be sufficiently reduced because refresh operationbecomes unnecessary or the frequency of refresh operation can beextremely tow. Moreover, stored data can be retained for a long timeeven when power is not supplied (note that a potential is preferablyfixed).

Furthermore, in the semiconductor device described in this embodiment, ahigh voltage is not needed for writing data and there is no problem ofdeterioration of elements. Unlike in a conventional nonvolatile memory,for example, it is not necessary to inject and extract electrons intoand from a floating gate; thus, a problem such as deterioration of agate insulating film is not caused at all. That is, the semiconductordevice of the disclosed invention does not have a limit on the number oftimes data can be rewritten, which is a problem of a conventionalnonvolatile memory, and the reliability thereof is drastically improved.Furthermore, data is written depending on the state of the transistor(on or off), whereby high-speed operation can be easily achieved.

The memory device described in this embodiment can also be used in anLSI such as a central processing unit (CPU), a digital signal processor(DSP), a custom LSI, or a programmable logic device (PLD), and a radiofrequency (RF) tag, for example.

The structures, methods, and the like described in this embodiment canbe used as appropriate in combination with any of the structures,methods, and the like described in other embodiments.

Embodiment 5

In this embodiment, a central processing unit (CPU) including the memorydevice described in Embodiment 4 will be described.

FIG. 18 is a block diagram illustrating a configuration example of a CPUat least partly including any of the transistors described in the aboveembodiments as a component.

The CPU illustrated in FIG. 18 includes, over a substrate 1190, anarithmetic logic unit (ALU) 1191, an ALU controller 1192, an instructiondecoder 1193, an interrupt controller 1194, a timing controller 1195, aregister 1196, a register controller 1197, a bus interface 1198 (BUSI/F), a rewritable ROM 1199, and a ROM interface (ROM I/F) 1189. Asemiconductor substrate, an SOI substrate, a glass substrate, or thelike is used as the substrate 1190. The ROM 1199 and the ROM interface1189 may be provided over a separate chip. Needless to say, the CPU inFIG. 18 is just an example in which the configuration is simplified, andan actual CPU may have a variety of configurations depending on theapplication. For example, the CPU may have the following configuration:a structure including the CPU illustrated in FIG. 18 or an arithmeticcircuit is considered as one core; a plurality of the cores areincluded; and the cores operate in parallel. The number of bits that theCPU can process in an internal arithmetic circuit or in a data bus canbe 8, 16, 32, or 64, for example.

An instruction that is input to the CPU through the bus interface 1198is input to the instruction decoder 1193 and decoded therein, and then,input to the ALU controller 1192, the interrupt controller 1194, theregister controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the registercontroller 1197, and the timing controller 1195 conduct various controlsin accordance with the decoded instruction. Specifically, the ALUcontroller 1192 generates signals for controlling the operation of theALU 1191. While the CPU is executing a program, the interrupt controller1194 judges an interrupt request from an external input/output device ora peripheral circuit on the basis of its priority or a mask state, andprocesses the request. The register controller 1197 generates an addressof the register 1196, and reads/writes data from/to the register 1196 inaccordance with the state of the CPU.

The timing controller 1195 generates signals for controlling operationtimings of the ALU 1191, the ALU controller 1192, the instructiondecoder 1193, the interrupt controller 1194, and the register controller1197. For example, the timing controller 1195 includes an internal clockgenerator for generating an internal clock signal based on a referenceclock signal, and supplies the internal clock signal to the abovecircuits.

In the CPU illustrated in FIG. 18, a memory cell is provided in theregister 1196. For the memory cell of the register 1196, any of thetransistors described in Embodiment 1 or the memory devices described inEmbodiment 2 can be used.

In the CPU illustrated in FIG. 18, the register controller 1197 selectsoperation of retaining data in the register 1196 in accordance with aninstruction from the ALU 1191. That is, the register controller 1197selects whether data is retained by a flip-flop or by a capacitor in thememory cell included in the register 1196. When data retaining by theflip-flop is selected, a power supply voltage is supplied to the memorycell in the register 1196. When data retaining by the capacitor isselected, the data is rewritten in the capacitor, and supply of thepower supply voltage to the memory cell in the register 1196 can bestopped.

The structures, methods, and the like described in this embodiment canbe used as appropriate in combination with any of the structures,methods, and the like described in other embodiments.

Embodiment 6

The semiconductor device of one embodiment of the present invention canbe used for display devices, personal computers, or image reproducingdevices provided with recording media (typically, devices whichreproduce the content of recording media such as digital versatile discs(DVDs) and have displays for displaying the reproduced images). Otherexamples of electronic devices that can be equipped with thesemiconductor device of one embodiment of the present invention arecellular phones, game machines including portable game machines,portable data terminals, e-book readers, cameras such as video camerasand digital still cameras, goggle-type displays (head mounted displays),navigation systems, audio reproducing devices (e.g., car audio systemsand digital audio players), copiers, facsimiles, printers, multifunctionprinters, automated teller machines (ATM), and vending machines. FIGS.19A to 19F illustrate specific examples of these electronic devices.

FIG. 19A illustrates a portable game machine, which includes a housing901, a housing 902, a display portion 903, a display portion 904, amicrophone 905, a speaker 906, an operation key 907, a stylus 908, andthe like. Although the portable game machine in FIG. 19A has the twodisplay portions 903 and 904, the number of display portions included ina portable game machine is not limited to this.

FIG. 19B illustrates a cellular phone, which is provided with a housing911, a display portion 916, operation buttons 914, an externalconnection port 913, a speaker 917, a microphone 912, and the like. Whenthe display portion 916 of the cellular phone illustrated in FIG. 19B istouched with a finger or the like, data can be input. Further,operations such as making a call and inputting a character can beperformed by touch on the display portion 916 with a finger or the like.The power can be turned on or off with the operation button 914. Inaddition, types of images displayed on the display portion 916 can beswitched; for example, switching images from a mail creation screen to amain menu screen is performed with the operation button 914.

FIG. 19C illustrates a notebook personal computer, which includes ahousing 921, a display portion 922, a keyboard 923, a pointing device924, and the like.

FIG. 19D illustrates an electric refrigerator-freezer, which includes ahousing 931, a refrigerator door 932, a freezer door 933, and foe like.

FIG. 19E illustrates a video camera, which includes a housing 941, ahousing 942, a display portion 943, operation keys 944, a lens 945, ajoint 946, and the like. The operation keys 944 and the lens 945 areprovided in the housing 941, and the display portion 943 is provided inthe housing 942. The housing 941 and the housing 942 are connected toeach other with the joint 946, and the angle between the housing 941 andthe housing 942 can be changed with the joint 946. Images displayed onthe display portion 943 may be switched in accordance with the angle atthe joint 946 between the housing 941 and the housing 942.

FIG. 19F illustrates a car, which includes a car body 951, wheels 952, adashboard 953, lights 954, and the like.

Note that this embodiment can be combined with any of the otherembodiments and examples in this specification as appropriate.

Embodiment 7

In this embodiment, application examples of an RF tag that can be formedusing the semiconductor device of one embodiment of foe presentinvention will be described with reference to FIGS. 20A to 20F. The RFtag is widely used and can be provided for, for example, products suchas bills, coins, securities, bearer bonds, documents (e.g., driver'slicenses or resident's cards, see FIG. 20A), recording media (e.g., DVDsor video tapes, sec FIG. 20B), packaging containers (e.g., wrappingpaper or bottles, see FIG. 20C), vehicles (e.g., bicycles, see FIG.20D), personal belongings (e.g., bags or glasses), foods, plants,animals, human bodies, clothing, household goods, medical supplies suchas medicine and chemicals, and electronic devices (e.g., liquid crystaldisplay devices, EL display devices, television sets, or cellularphones), or tags on products (sec FIGS. 20E and 20F).

An RF tag 4000 of one embodiment of the present invention is fixed to aproduct by being attached to a surface thereof or embedded therein. Forexample, the RF tag 4000 is fixed to each product by being embedded inpaper of a book, or embedded in an organic resin of a package. Since theRF tag 4000 of one embodiment of the present invention can be reduced insize, thickness, and weight, it can be fixed to a product withoutspoiling the design of the product. Furthermore, bills, coins,securities, bearer bonds, documents, or the like can have anidentification function by being provided with the RF tag 4000 of oneembodiment of the present invention, and the identification function canbe utilized to prevent counterfeiting. Moreover, the efficiency of asystem such as an inspection system can be improved by providing the RFtag of one embodiment of the present invention for packaging containers,recording media, personal belongings, foods, clothing, household goods,electronic devices, or the like. Vehicles can also have higher securityagainst theft or the like by being provided with the RF tag of oneembodiment of the present invention.

As described above, by using the RF tag of one embodiment of the presentinvention for each application described in this embodiment, power foroperation such as writing or reading of data can be reduced, whichresults in an increase in the maximum communication distance. Moreover,data can be held for an extremely long period even in the state wherepower is not supplied; thus, the RF tag can be preferably used forapplication in which data is not frequently written or read.

Next, an example of use of a display device which can include thesemiconductor device of one embodiment of the present invention will bedescribed. In one example, a display device includes a pixel. The pixelincludes a transistor and a display element, for example. Alternatively,the display device includes a driver circuit for driving foe pixel. Thedriver circuit includes a transistor, for example. As these transistors,any of the transistors described in the other embodiments can beemployed, for example.

In this specification and the like, for example, a display element, adisplay device which is a device including a display element, alight-emitting element, and a light-emitting device which is a deviceincluding a light-emitting element can employ a variety of modes or caninclude a variety of elements. The display element, the display device,the light-emitting element, or the light-emitting device includes atleast one of an electroluminescence (EL) element (e.g., an EL elementincluding organic and inorganic materials, an organic EL element, or aninorganic EL element), an LED (e.g., a white LED, a red LED, a greenLED, or a blue LED), a transistor (a transistor that emits lightdepending on a current), an electron emitter, a liquid crystal element,electronic ink, an electrophoretic element, a grating light valve (GLV),a plasma display panel (PDF), a display element using a micro electromechanical system (MEMS), a digital micromirror device (DMD), a digitalmicro shutter (DMS), MIRASOL (registered trademark), an interferometricmodulator display (IMOD) element, a MEMS shutter display element, anoptical-interference-type MEMS display element, an electrowettingelement, a piezoelectric ceramic display, a display element including acarbon nanotube, and the like. Other than the above, a display mediumwhose contrast, luminance, reflectance, transmittance, or the tike ischanged by electrical or magnetic effect may be included. Examples of adisplay device including an EL element include an EL display. Examplesof a display device including an electron emitter include a fieldemission display (FED) and an SED-type flat panel display (SED:surface-conduction electron-emitter display). Examples of a displaydevice including a liquid crystal element include a liquid crystaldisplay (e.g., a transmissive liquid crystal display, a transflectiveliquid crystal display, a reflective liquid crystal display, adirect-view liquid crystal display, or a projection liquid crystaldisplay). Examples of a display device including electronic ink.Electronic Liquid Powder (registered trademark), or an electrophoreticelement include electronic paper. In the case of a transflective liquidcrystal display or a reflective liquid crystal display, some or all ofpixel electrodes function as reflective electrodes. For example, some orall of pixel electrodes are formed to contain aluminum, silver, or thelike. In such a case, a memory circuit such as an SRAM can be providedunder the reflective electrodes, leading to lower power consumption.

Note that this embodiment can be combined with any of the otherembodiments and examples in this specification as appropriate.

Embodiment 8

In this embodiment, a structure of an oxide semiconductor filmapplicable to the semiconductor 662 will be described.

In this specification, the term “parallel” indicates that the angleformed between two straight lines is greater than or equal to −10° andless than or equal to 10°, and accordingly also includes the case wherethe angle is greater than or equal to −5° and less than or equal to 5°.In addition, the term “substantially parallel” indicates that the angleformed between two straight lines is greater than or equal to −30° andless than or equal to 30°. The term “perpendicular” indicates that theangle formed between two straight lines is greater titan or equal to 80°and less than or equal to 100°, and accordingly also includes the casewhere the angle is greater than or equal to 85° and less than or equalto 95°. In addition, the term “substantially perpendicular” indicatesthat the angle formed between two straight lines is greater than orequal to 60° and less than or equal to 120°.

In this specification, trigonal and rhombohedral crystal systems areincluded in a hexagonal crystal system.

<<Structure of Oxide Semiconductor>>

The structure of an oxide semiconductor will be described below.

An oxide semiconductor is classified into a single crystal oxidesemiconductor and a non-single-crystal oxide semiconductor. Examples ofa non-single-crystal oxide semiconductor include a c-axis alignedcrystalline oxide semiconductor (CAAC-OS), a polycrystal line oxidesemiconductor, a nanocrystalline oxide semiconductor (nc-OS), anamorphous-like oxide semiconductor (a-like OS), and an amorphous oxidesemiconductor.

From another perspective, an oxide semiconductor is classified into anamorphous oxide semiconductor and a crystalline oxide semiconductor.Examples of a crystalline oxide semiconductor include a single crystaloxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor,and an nc-OS.

It is known that an amorphous structure is generally defined as beingmetastable and unfixed, and being isotropic and having no non-uniformstructure. In other words, an amorphous structure has a flexible bondangle and a short-range order but does not have a long-range order.

This means that an inherently stable oxide semiconductor cannot beregarded as a completely amorphous oxide semiconductor. Moreover, anoxide semiconductor that is not isotropic (e.g., an oxide semiconductorthat has a periodic structure in a microscopic region) cannot beregarded as a completely amorphous oxide semiconductor. Note that ana-like OS has a periodic structure in a microscopic region, but at thesame time has a void and has an unstable structure. For this reason, ana-like OS has physical properties similar to those of an amorphous oxidesemiconductor.

<CAAC-OS>

First, a CAAC-OS will be described.

The CAAC-OS is one of oxide semiconductors having a plurality of c-axisaligned crystal parts (also referred to as pellets).

In a combined analysis image (also referred to as a high-resolution TEMimage) of a bright-field image and a diffraction pattern of a CAAC-OS,which is obtained using a transmission electron microscope (TEM), aplurality of pellets can be observed. However, in the high-resolutionTEM image, a boundary between pellets, that is, a grain boundary is notclearly observed. Thus, in the CAAC-OS, a reduction in electron mobilitydue to the grain boundary is less likely to occur.

A CAAC-OS observed with TEM will be described below. FIG. 21A shows ahigh-resolution TEM image of a cross section of the CAAC-OS which isobserved from a direction substantially parallel to the sample surface.The high-resolution TEM image is obtained with a spherical aberrationcorrector function. The high-resolution TEM image obtained with aspherical aberration corrector function is particularly referred to as aCs-corrected high-resolution TEM image. The Cs-corrected high-resolutionTEM image can be obtained with, for example, an atomic resolutionanalytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 21B is an enlarged Cs-corrected high-resolution TEM image of aregion (1) in FIG. 21A. FIG. 21B shows that metal atoms are arranged ina layered manner in a pellet. Each metal atom layer has a configurationreflecting unevenness of a surface over which the CAAC-OS is formed(hereinafter, the surface is referred to as a formation surface) or atop surface of the CAAC-OS, and is arranged parallel to the formationsurface or the top surface of the CAAC-OS.

As shown in FIG. 21B, the CAAC-OS has a characteristic atomicarrangement. The characteristic atomic arrangement is denoted by anauxiliary line in FIG. 21C. FIGS. 21B and 21C prove that the size of apellet is greater than or equal to 1 nm or greater than or equal to 3nm, and the size of a space caused by tilt of the pellets isapproximately 0.8 nm. Therefore, the pellet can also be referred to as ananocrystal (nc). Furthermore, the CAAC-OS can also be referred to as anoxide semiconductor including c-axis aligned nanocrystals (CANC).

Here, according to the Cs-corrected high-resolution TEM images, theschematic arrangement of pellets 5100 of a CAAC-OS over a substrate 5120is illustrated by such a structure in which bricks or blocks are stacked(see FIG. 21D). The part in which the pellets are tilted as observed inFIG. 21C corresponds to a region 5161 shown in FIG. 21D.

FIG. 22A shows a Cs-corrected high-resolution TEM image of a plane ofthe CAAC-OS observed from a direction substantially perpendicular to thesample surface. FIGS. 22B, 22C, and 22D are enlarged Cs-correctedhigh-resolution TEM images of regions (1), (2), and (3) in FIG. 22A,respectively. FIGS. 22B, 22C, and 22D indicate that metal atoms arearranged in a triangular, quadrangular, or hexagonal configuration in apellet. However, there is no regularity of arrangement of metal atomsbetween different pellets.

Next, a CAAC-OS analyzed by X-ray diffraction (XRD) will be described.

For example, when the structure of a CAAC-OS including an InGaZnO₄crystal is analyzed by an out-of-plane method, a peak appears at adiffraction angle (2θ) of around 31° as shown in FIG. 23A. This peak isattributed to the (009) plane of the InGaZnO₄ crystal, which indicatesthat crystals in the CAAC-OS have c-axis alignment, and that the c-axesare aligned in a direction substantially perpendicular to the formationsurface or the top surface of the CAAC-OS.

Note that in structural analysis of the CAAC-OS by an out-of-planemethod, another peak may appear when 2θ is around 36°, in addition tothe peak at 2θ of around 31°. The peak at 2θ of around 36° indicatesthat a crystal having no c-axis alignment is included in part of theCAAC-OS. It is preferable that in the CAAC-OS analyzed by anout-of-plane method, a peak appear when 2θ is around 31° and that a peaknot appear when 2θ is around 36°.

On the other hand, in structural analysts of the CAAC-OS by an in-planemethod in which an X-ray beam is incident on a sample in a directionsubstantially perpendicular to the c-axis, a peak appears when 2θ isaround 56°. This peak is attributed to the (110) plane of the InGaZnO₄crystal. In the case of the CAAC-OS, when analysis (ϕ scan) is performedwith 2θ fixed at around 56° and with the sample rotated using a normalvector of the sample surface as an axis (ϕ axis), as shown in FIG. 23B,a peak is not clearly observed. In contrast, in the case of a singlecrystal oxide semiconductor of InGaZnO₄, when ϕ scan is performed with2θ fixed at around 56°, as shown in FIG. 23C, six peaks which areattributed to crystal planes equivalent to the (110) plane are observed.Accordingly, the structural analysis using XRD shows that the directionsof a-axes and b-axes are irregularly oriented in the CAAC-OS.

Next, a CAAC-OS analyzed by electron diffraction will be described. Forexample, when an electron beam with a probe diameter of 300 nm isincident on a CAAC-OS including an InGaZnO₄ crystal in a directionparallel to the sample surface, a diffraction pattern (also referred toas a selected-area transmission electron diffraction pattern) shown inFIG. 24A can be obtained. In this diffraction pattern, spots attributedto the (009) plane of an InGaZnO₄ crystal are included. Thus, theelectron diffraction also indicates that pellets included in the CAAC-OShave c-axis alignment and that the c-axes are aligned in a directionsubstantially perpendicular to the formation surface or the top surfaceof the CAAC-OS. Meanwhile, FIG. 24B shows a diffraction pattern obtainedin such a manner that an electron beam with a probe diameter of 300 nmis incident on the same sample in a direction perpendicular to thesample surface. As shown in FIG. 24B, a ring-like diffraction pattern isobserved. Thus, the electron diffraction also indicates that the a-axesand b-axes of the pellets included in the CAAC-OS do not have regularalignment. The first ring in FIG. 24B is considered to be attributed tothe (010) plane, the (100) plane, and the like of the InGaZnO₄ crystal.The second ring in FIG. 24B is considered to be attributed to the (110)plane and the like.

As described above, the CAAC-OS is an oxide semiconductor with highcrystallinity. Entry of impurities, formation of defects, or the likemight decrease the crystallinity of an oxide semiconductor. This meansthat the CAAC-OS has small amounts of impurities and defects (e.g.,oxygen vacancies).

Note that the impurity means an element other than the main componentsof the oxide semiconductor, such as hydrogen, carbon, silicon, or atransition metal element. For example, an element (specifically, siliconor the like) having higher strength of bonding to oxygen than a metalelement included in an oxide semiconductor extracts oxygen from theoxide semiconductor, which results in disorder of the atomic arrangementand reduced crystallinity of the oxide semiconductor. A heavy metal suchas iron or nickel, argon, carbon dioxide, or the like has a large atomicradius (or molecular radius), and thus disturbs the atomic arrangementof the oxide semiconductor and decreases crystallinity.

The characteristics of an oxide semiconductor having impurities ordefects might be changed by light, heat, or the like. Impuritiescontained in the oxide semiconductor might serve as carrier traps orcarrier generation sources, for example. Furthermore, an oxygen vacancyin the oxide semiconductor might serve as a carrier trap or serve as acarrier generation source when hydrogen is captured therein.

The CAAC-OS having small amounts of impurities and oxygen vacancies isan oxide semiconductor with low carrier density. Such an oxidesemiconductor is referred to as a highly purified intrinsic orsubstantially highly purified intrinsic oxide semiconductor. A CAAC-OShas a low impurity concentration and a low density of defect states.Thus, the CAAC-OS can be referred to as an oxide semiconductor havingstable characteristics.

<nc-OS>

Next, an nc-OS will be described.

An nc-OS has a region in which a crystal part is observed and a regionin which a crystal part is not clearly observed in a high-resolution TEMimage. In most cases, the size of a crystal part included in the nc-OSis greater than or equal to 1 nm and less than or equal to 10 nm, orgreater than or equal to 1 nm and less than or equal to 3 nm. Note thatan oxide semiconductor including a crystal part whose size is greaterthan 10 nm and less than or equal to 100 nm is sometimes referred to asa microcrystalline oxide semiconductor. In a high-resolution IBM imageof the nc-OS, for example, a grain boundary is not clearly observed insome cases. Note that there is a possibility that the origin of thenanocrystal is the same as that of a pellet in a CAAC-OS. Therefore, acrystal part of the nc-OS may be referred to as a pellet in thefollowing description.

In the nc-OS, a microscopic region (for example, a region with a sizegreater than or equal to 1 nm and less than of equal to 10 nm, inparticular, a region with a size greater than or equal to 1 nm and lessthan or equal to 3 nm) has a periodic atomic arrangement. There is noregularity of crystal orientation between different pellets in thenc-OS. Thus, the orientation of the whole film is not ordered.Accordingly, the nc-OS cannot be distinguished from an a-like OS or anamorphous oxide semiconductor, depending on an analysis method. Forexample, when the nc-OS is analyzed by an out-of-plane method using anX-ray beam having a diameter larger than the size of a pellet, a peakwhich shows a crystal plane does not appear. Furthermore, a diffractionpattern like a halo pattern is observed when the nc-OS is subjected toelectron diffraction using an electron beam with a probe diameter (e.g.,50 nm or larger) that is larger than the size of a pellet. Meanwhile,spots appear in a nanobeam electron diffraction pattern of the nc-OSwhen an electron beam having a probe diameter close to or smaller thanthe size of a pellet is applied. Moreover, in a nanobeam electrondiffraction pattern of the nc-OS, bright regions in a circular (ring)pattern are shown in some cases. Also in a nanobeam electron diffractionpattern of the nc-OS, a plurality of spots is shown in a ring-likeregion in some cases.

Since there is no regularity of crystal orientation between the pellets(nanocrystals) as mentioned above, the nc-OS can also be referred to asan oxide semiconductor including random aligned nanocrystals (RANC) oran oxide semiconductor including non-aligned nanocrystals (NANC).

The nc-OS is an oxide semiconductor that has high regularity as comparedwith an amorphous oxide semiconductor. Therefore, the nc-OS is likely tohave a lower density of defect states than an a-like OS and an amorphousoxide semiconductor. Note that there is no regularity of crystalorientation between different pellets in the nc-OS. Therefore, the nc-OShas a higher density of defect states than the CAAC-OS.

<A-Like OS>

An a-like OS has a structure intermediate between those of the nc-OS andthe amorphous oxide semiconductor.

In a high-resolution TEM image of the a-like OS, a void may be observed.Furthermore, in the high-resolution TEM image, there are a region wherea crystal part is clearly observed and a region where a crystal part isnot observed.

The a-like OS has an unstable structure because it contains a void. Toverify that an a-like OS has an unstable structure as compared with aCAAC-OS and an nc-OS, a change in structure caused by electronirradiation is described below.

An a-like OS (referred to as Sample A), an nc-OS (referred to as SampleB), and a CAAC-OS (referred to as Sample C) are prepared as samplessubjected to electron irradiation. Each of the samples is an In—Ga—Znoxide.

First, a high-resolution cross-sectional TEM image of each sample isobtained. The high-resolution cross-sectional TEM images show that allthe samples have crystal parts.

Note that which part is regarded as a crystal part is determined asfollows. It is known that a unit cell of an InGaZnO₄ crystal has astructure in which nine layers including three In—O layers and sixGa—Zn—O layers are stacked in the c-axis direction. The distance betweenthe adjacent layers is equivalent to the lattice spacing on the (009)plane (also referred to as d value). The value is calculated to be 0.29nm from crystal structural analysis. Accordingly, a portion where thelattice spacing between lattice fringes is greater than or equal to 0.28nm and less than or equal to 0.30 nm is regarded as a crystal part ofInGaZnO₄. Each of lattice fringes corresponds to the a-b plane of theInGaZnO₄ crystal.

FIG. 25 shows change in the average size of crystal parts (at 22 pointsto 45 points) in each sample. Note that the crystal part sizecorresponds to the length of a lattice fringe. FIG. 25 indicates thatthe crystal part size in the a-like OS increases with an increase in thecumulative electron dose. Specifically, as shown by (1) in FIG. 25, acrystal part of approximately 1.2 nm (also referred to as an initialnucleus) at the start of TEM observation grows to a size ofapproximately 2.6 nm at a cumulative electron dose of 4.2×10⁸ e⁻/nm². Incontrast, the crystal part size in the nc-OS and the CAAC-OS showslittle change from the start of electron irradiation to a cumulativeelectron dose of 4.2×10⁸ e⁻/nm². Specifically, as shown by (2) and (3)in FIG. 25, the average crystal sizes in an nc-OS and a CAAC-OS areapproximately 1.4 nm and approximately 2.1 nm, respectively, regardlessof the cumulative electron dose.

In this manner, growth of the crystal part in the a-like OS is inducedby electron irradiation. In contrast, in the nc-OS and the CAAC-OS,growth of the crystal part is hardly induced by electron irradiation.Therefore, the a-like OS has an unstable structure as compared with thenc-OS and the CAAC-OS.

The a-like OS has a lower density than the nc-OS and the CAAC-OS becauseit contains a void. Specifically, the density of the a-like OS is higherthan or equal to 78.6% and lower than 92.3% of the density of the singlecrystal oxide semiconductor having the same composition. The density ofeach of the nc-OS and the CAAC-OS is higher than or equal to 92.3% andlower than 100% of the density of the single crystal oxide semiconductorhaving the same composition. It is difficult to deposit an oxidesemiconductor having a density of lower than 78% of the density of thesingle crystal oxide semiconductor.

For example, in the case of an oxide semiconductor having an atomicratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO₄ with arhombohedral crystal structure is 6.357 g/cm³. Accordingly, in the caseof the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, thedensity of the a-like OS is higher than or equal to 5.0 g/cm³ and lowerthan 5.9 g/cm³. For example, in the case of the oxide semiconductorhaving an atomic ratio of In:Ga:Zn=1:1:1, the density of each of thenc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm³ and lowerthan 6.3 g/cm³.

Note that there is a possibility that an oxide semiconductor having acertain composition cannot exist in a single crystal structure. In thatease, single crystal oxide semiconductors with different compositionsare combined at an adequate ratio, which makes it possible to calculatedensity equivalent to that of a single crystal oxide semiconductor withthe desired composition. The density of a single crystal oxidesemiconductor having the desired Composition can be calculated using aweighted average according to the combination ratio of the singlecrystal oxide semiconductors with different compositions. Note that itis preferable to use as few kinds of single crystal oxide semiconductorsas possible to calculate the density.

As described above, oxide semiconductors have various structures andvarious properties. Note that an oxide semiconductor may be a stackedlayer including two or more of an amorphous oxide semiconductor, ana-like OS, an nc-OS, and a CAAC-OS, for example.

<Deposition Model>

Examples of deposition models of a CAAC-OS and an nc-OS are describedbelow.

FIG. 26A is a schematic view of the inside of a deposition chamber wherea CAAC-OS is deposited by a sputtering method.

A target 5130 is attached to a backing plate. A plurality of magnets isprovided to face the target 5130 with the backing plate positionedtherebetween. The plurality of magnets generates a magnetic field. Asputtering method in which the disposition rate is increased byutilizing a magnetic field of magnets is referred to as a magnetronsputtering method.

The substrate 5120 is placed to face the target 5130, and the distance d(also referred to as a target-substrate distance (T-S distance)) isgreater than or equal to 0.01 m and less than or equal to 1 m,preferably greater titan or equal to 0.02 m and less than or equal to0.5 m. The deposition chamber is mostly filled with a deposition gas(e.g., an oxygen gas, an argon gas, or a mixed gas containing oxygen at5 vol % or higher) and the pressure in the deposition chamber iscontrolled to be higher than or equal to 0.01 Pa and lower than or equalto 100 Pa, preferably higher than or equal to 0.1 Pa and lower than orequal to 10 Pa. Here, discharge starts by application of a voltage at acertain value or higher to the target 5130, and plasma is observed. Themagnetic field forms a high-density plasma region in the vicinity of thetarget 5130. In the high-density plasma region, the deposition gas isionized, so that an ion 5101 is generated. Examples of the ion 5101include an oxygen cation (O⁺) and an argon cation (Ar⁺).

Here, the target 5130 has a polycrystalline structure which includes aplurality of crystal grains and in which a cleavage plane exists in atleast one crystal grain. FIG. 27A shows a structure of an InGaZnO₄crystal included in the target 5130 as an example. Note that FIG. 27Ashows a structure of the case where the InGaZnO₄ crystal is observedfrom a direction parallel to the b-axis. FIG. 27A indicates that oxygenatoms in a Ga—Zn—O layer are positioned close to those in an adjacentGa—Zn—O layer. The oxygen atoms have negative charge, whereby repulsiveforce is generated between the two Ga—Zn—O layers. As a result, theInGaZnO₄ crystal has a cleavage plane between the two adjacent Ga—Zn—Olayers.

The ion 5101 generated in the high-density plasma region is acceleratedtoward the target 5130 side by an electric field, and then, collideswith the target 5130. At this time, a pellet 5100 a and a pellet 5100 bwhich are flat-plate-like (pellet-like) sputtered particles areseparated and sputtered from the cleavage plane. Note that structures ofthe pellet 5100 a and the pellet 5100 b may be distorted by an impact ofcollision of the ion 5101.

The pellet 5100 a is a flat-plate-like (pellet-like) sputtered particlehaving a triangle plane, e.g., regular triangle plane. The pellet 5100 bis a flat-plate-like (pellet-like) sputtered panicle having a hexagonplane, e.g., regular hexagon plane. Note that flat-plate-like(pellet-like) sputtered particles such as the pellet 5100 a and thepellet 5100 b are collectively called pellets 5100. The shape of a flatplane of the pellet 5100 is not limited to a triangle or a hexagon. Forexample, the flat plane may have a shape formed by combining two or moretriangles. For example, a quadrangle (e.g., rhombus) may be formed bycombining two triangles (e.g., regular triangles).

The thickness of the pellet 5100 is determined depending on the kind ofdeposition gas and the like. The thicknesses of the pellets 5100 arepreferably uniform; the reason for this is described later. In addition,the sputtered particle preferably has a pellet shape with a smallthickness as compared to a dice shape with a large thickness. Forexample, the thickness of the pellet 5100 is greater than or equal to0.4 nm and less than or equal to 1 nm, preferably greater than or equalto 0.6 run and less than or equal to 0.8 nm. In addition, for example,the width of the pellet 5100 is greater than or equal to 1 nm and lessthan or equal to 3 nm, preferably greater than or equal to 1.2 nm andless than or equal to 2.5 nm. The pellet 5100 corresponds to the initialnucleus in the description of (1) in FIG. 25. For example, when the ion5101 collides with the target 5130 including an In—Ga—Zn oxide, thepellet 5100 that includes three layers of a Ga—Zn—O layer, an In—Olayer, and a Ga—Zn—O layer as shown in FIG. 27B is separated. Note thatFIG. 27C shows the structure of the separated pellet 5100 which isobserved from a direction parallel to the c-axis. The pellet 5100 has ananometer-sized sandwich structure including two Ga—Zn—O layers (piecesof bread) and an In—O layer (filling).

The pellet 5100 may receive a charge when passing through the plasma, sothat side surfaces thereof are negatively or positively charged. In thepellet 5100, an oxygen atom positioned on its side surface may benegatively charged. When the side surfaces are charged with the samepolarity, charges repel each other, and accordingly, the pellet 5100 canmaintain a flat-plate (pellet) shape. In the case where a CAAC-OS is anIn—Ga—Zn oxide, there is a possibility that an oxygen atom bonded to anindium atom is negatively charged. There is another possibility that anoxygen atom bonded to an indium atom, a gallium atom, or a zinc atom isnegatively charged. In addition, the pellet 5100 may grow by beingbonded with an indium atom, a gallium atom, a zinc atom, an oxygen atom,or the like when passing through plasma. A difference in size between(2) and (1) in FIG. 25 corresponds to the amount of growth in plasma.Here, in the case where the temperature of the substrate 5120 is ataround room temperature, the pellet 5100 on the substrate 5120 hardlygrows; thus, an nc-OS is formed (see FIG. 26B). An nc-OS can bedeposited when the substrate 5120 has a large size because thedeposition of an nc-OS can be carried out at room temperature. Note thatin order that the pellet 5100 grows in plasma, it is effective toincrease deposition power in sputtering. High deposition power canstabilize the structure of the pellet 5100.

As shown in FIGS. 26A and 26B, the pellet 5100 flies like a kite inplasma and flutters up to the substrate 5120. Since the pellets 5100 arecharged, when the pellet 5100 gets close to a region where anotherpellet 5100 has already been deposited, repulsion is generated. Here,above the substrate 5120, a magnetic field in a direction parallel tothe top surface of the substrate 5120 (also referred to as a horizontalmagnetic field) is generated. A potential difference is given betweenthe substrate 5120 and the target 5130, and accordingly, a current flowsfrom the substrate 5120 toward the target 5130. Thus, the pellet 5100 isgiven a force (Lorentz force) on the top surface of the substrate 5120by an effect of the magnetic field and the current. This is explainablewith Fleming's left-hand rule.

The mass of the pellet 5100 is larger than that of an atom. Therefore,to move the pellet 5100 over the top surface of the substrate 5120, itis important to apply some force to the pellet 5100 from the outside.One kind of the force may be force which is generated by the action of amagnetic field and a current. In order to apply a sufficient force tothe pellet 5100 so that the pellet 5100 moves over a top surface of thesubstrate 5120, it is preferable to provide, on the top surface of thesubstrate 5120, a region where the magnetic field in a directionparallel to the top surface of the substrate 5120 is 10 G or higher,preferably 20 G or higher, further preferably 30 G or higher, and stillfurther preferably 50 G or higher. Alternatively, it is preferable toprovide, on the top surface of the substrate 5120, a region where themagnetic field in a direction parallel to the top surface of thesubstrate 5120 is 1.5 times or higher, preferably twice or higher,further preferably 3 times or higher, and still further preferably 5times or higher as high as the magnetic field in a directionperpendicular to the top surface of the substrate 5120.

At this time, the magnets and the substrate 5120 are moved or rotatedrelatively, whereby the direction of the horizontal magnetic field onthe top surface of the substrate 5120 continues to change. Therefore,the pellet 5100 can be moved in various directions on the top surface ofthe substrate 5120 by receiving forces in various directions.

Furthermore, as shown in FIG. 26A, when the substrate 5120 is heated,resistance between the pellet 5100 and the substrate 5120 due tofriction or the like is low. As a result, the pellet 5100 glides abovethe top surface of the substrate 5120. The glide of the pellet 5100 iscaused in a state where its flat plane faces the substrate 5120. Then,when the pellet 5100 reaches the side surface of another pellet 5100that has been already deposited, the side surfaces of the pellets 5100are bonded. At this time, the oxygen atom on the side surface of thepellet 5100 is released. With the released oxygen atoms, oxygenvacancies in a CAAC-OS might be filled; thus, the CAAC-OS has a lowdensity of defect states. Note that the temperature of the top surfaceof the substrate 5120 is, for example, higher than or equal to 100° C.and lower than 500° C., higher than or equal to 150° C. and lower than450° C., or higher than or equal to 170° C. and lower than 400° C.Hence, even when the substrate 5120 has a large size, it is possible todeposit a CAAC-OS.

Furthermore, the pellet 5100 is heated on the substrate 5120, wherebyatoms are rearranged, and the structure distortion caused by thecollision of the ion 5101 can be reduced. The pellet 5100 whosestructure distortion is reduced is substantially single crystal. Evenwhen the pellets 5100 are heated after being bonded, expansion andcontraction of the pellet 5100 itself hardly occur, which is caused byturning the pellet 5100 into substantially single crystal. Thus,formation of defects such as a grain boundary due to expansion of aspace between the pellets 5100 can be prevented, and accordingly,generation of crevasses can be prevented.

The CAAC-OS docs not have a structure like a board of a single crystaloxide semiconductor but has arrangement with a group of pellets 5100(nanocrystals) like stacked bricks or blocks. Furthermore, a grainboundary docs not exist, between the pellets 5100. Therefore, even whendeformation such as shrink occurs in the CAAC-OS Owing to heating duringdeposition, heating or bending after deposition, it is possible torelieve local stress or release distortion. Therefore, this structure issuitable for a flexible semiconductor device. Note that the nc-OS hasarrangement in which pellets 5100 (nanocrystals) are randomly stacked.

When the target 5130 is sputtered with the ion 5101, in addition to thepellets 5100, zinc oxide or the like may be separated. The zinc oxide islighter than the pellet 5100 and thus reaches the top surface of thesubstrate 5120 before the pellet 5100. As a result, the zinc oxide formsa zinc oxide layer 5102 with a thickness greater than or equal to 0.1 nmand less than or equal to 10 nm, greater than or equal to 0.2 nm andless than or equal to 5 nm, or greater than or equal to 0.5 nm and lessthan or equal to 2 nm. FIGS. 28A to 28D are cross-sectional schematicviews.

As illustrated in FIG. 28A, a pellet 5105 a and a pellet 5105 b aredeposited over the zinc oxide layer 5102. Here, side surfaces of thepellet 5105 a and the pellet 5105 b are in contact with each other. Inaddition, a pellet 5105 c is deposited over the pellet 5105 b, and thenglides over the pellet 5105 b. Furthermore, a plurality of particles5103 separated from the target together with the zinc oxide iscrystallized by heat from the substrate 5120 to form a region 5105 a 1on another side surface of the pellet 5105 a. Note that the plurality ofparticles 5103 may contain oxygen, zinc, indium, gallium, or the like.

Then, as illustrated in FIG. 28B, lire region 5105 a 1 grows to part ofthe pellet 5105 a to form a pellet 5105 a 2. In addition, a side surfaceof the pellet 5105 c is in contact with another side surface of thepellet 5105 b.

Next, as illustrated in FIG. 28C, a pellet 5105 d is deposited over thepellet 5105 a 2 and the pellet 5105 b, and then glides over the pellet5105 a 2 and the pellet 5105 b. Furthermore, a pellet 5105 c glidestoward another side surface of the pellet 5105 c over the zinc oxidelayer 5102.

Then, as illustrated in FIG. 28D, the pellet 5105 d is placed so that aside surface of the pellet 5105 d is in contact with a side surface ofthe pellet 5105 a 2. Furthermore, a side surface of the pellet 5105 e isin contact with another side surface of the pellet 5105 c. A pluralityof particles 5103 separated from the target 5130 together with the zincoxide is crystallized by heat from the substrate 5120 to form a region5105 d 1 on another side surface of the pellet 5105 d.

As described above, deposited pellets are placed to be in contact witheach other and then growth is caused at side surfaces of the pellets,whereby a CAAC-OS is formed over the substrate 5120. Therefore, eachpellet of the CAAC-OS is larger than that of the nc-OS. A difference insize between (3) and (2) in FIG. 25 corresponds to the amount of growthafter deposition.

When spaces between pellets are extremely small, the pellets may form alarge pellet. The large pellet has a single crystal structure. Forexample, the size of the pellet may be greater than or equal to 10 nmand less than or equal to 200 nm, greater than or equal to IS nm andless than or equal to 100 nm, or greater than or equal to 20 nm and lessthan or equal to 50 nm, when seen from the above. In this case, in anoxide semiconductor used for a minute transistor, a channel formationregion might be fit inside the large pellet. Therefore, the regionhaving a single crystal structure can be used as the channel formationregion. Furthermore, when the size of the pellet is increased, theregion having a single crystal structure can be used as the channelformation region, the source region, and the drain region of thetransistor.

In this manner, when the channel formation region or the like of thetransistor is formed in a region having a single crystal structure, thefrequency characteristics of the transistor can be increased in somecases.

As shown in such a model, the pellets 5100 are considered to bedeposited on the substrate 5120. Thus, a CAAC-OS can be deposited evenwheat a formation surface does not have a crystal structure; therefore,a growth mechanism in this case is different from epitaxial growth. Inaddition, laser crystallization is not needed for formation of aCAAC-OS, and a uniform film can be formed even over a large-sized glasssubstrate or the like. For example, even when the top surface (formationsurface) of the substrate 5120 has an amorphous structure (e.g., the topsurface is formed of amorphous silicon oxide), a CAAC-OS can be formed.

In addition, it is found that in formation of foe CAAC-OS, the pellets5100 are arranged in accordance with the top surface shape of thesubstrate 5120 that is the formation surface even when the formationsurface has unevenness. For example, in the case where the top surfaceof the substrate 5120 is flat at the atomic level, the pellets 5100 arearranged so that flat planes parallel to foe a-b plane face downwards.In foe case where the thicknesses of the pellets 5100 are uniform, alayer with a uniform thickness, flatness, and high crystallinity isformed. By stacking n layers (n is a natural number), foe CAAC-OS can beobtained.

In the case where the top surface of the substrate 5120 has unevenness,a CAAC-OS in which n layers (n is a natural number) in each of which thepellets 5100 are arranged along the unevenness are stacked is formed.Since the substrate 5120 has unevenness, a gap is easily generatedbetween foe pellets 5100 in the CAAC-OS in some cases. Note that, evenin such a case, owing to intermolecular force, the pellets 5100 arearranged so that a gap between the pellets is as small as possible evenon the unevenness surface. Therefore, even when the formation surfacehas unevenness, a CAAC-OS with high crystallinity can be obtained.

Since a CAAC-OS is deposited in accordance with such a model, thesputtered particle preferably has a pellet shape with a small thickness.Note that when the sputtered particles have a dice shape with a largethickness, planes facing the substrate 5120 vary; thus, the thicknessesand orientations of foe crystals cannot be uniform in some cases.

According to foe deposition model described above, a CAAC-OS with highcrystallinity can be formed even on a formation surface with anamorphous structure.

Example 1

As described above, a transistor whose channel contains an oxidesemiconductor (hereinafter, such a transistor is referred to as an “OStransistor” in some cases) has an extremely low off-state current. Thecombination of an OS transistor and a Si transistor can provide acircuit having functions and capability that a circuit only including Sitransistors docs not have. In this example, a memory circuit includingan OS transistor and a Si transistor was actually fabricated to confirmthat an off-state current of a minute OS transistor can be representedby Formula (4) given by the above-mentioned stretched exponentialfunction.

<<Prototyped Circuit>> <Circuit Configuration>

FIG. 30 is a circuit diagram of a prototyped circuit. A circuit MC10illustrated in FIG. 30 was designed to be a memory cell of a randomaccess memory. The circuits illustrated in FIG. 30 and FIG. 3 havesimilar circuit configurations; thus, the same reference numerals areused for the same components. A transistor MW0, a transistor MR1, atransistor MR2, and a capacitor CS1 in FIG. 30 correspond to thetransistor M0, the transistor M1, the transistor M2, and the capacitorCS in FIG. 3, respectively. In the circuit MC10 illustrated in FIG. 30,the transistor MW0 and the capacitor CS1 formed a holding circuit RC0.The transistor MW0 was an OS transistor, and the transistors MR1 and MR2were n-channel Si transistors.

The designed channel lengths L and channel widths W of the transistorsin the circuit MC10 were as follows: L/W of the transistor MW0 was 60/60nm and L/W of each of the transistors MR1 and MR2 was 180/60 nm.

<Device Structure>

FIG. 31 shows a device structure of the circuit MC10. FIG. 31 is across-sectional view of the circuit MC10 for easy understanding of thelayered structure, the connection, and the like, and is not across-sectional view taken along a specific line.

The transistors MR1 and MR2 are planar transistors and are formed on anSOI semiconductor substrate. Reference numerals 500 and 501 designate asingle crystal silicon wafer and a silicon oxide layer, respectively.Channel regions, source regions, and drain regions of the transistorsMR1 and MR2 are in one single crystal silicon layer 520.

The transistor MW0 and the capacitor CS1 are stacked over thetransistors MR1 and MR2. The prototyped circuit MC10 includes insulatinglayers 502 to 511 and seven wiring tiers. The transistors (MW0, MR1, andMR2) and the capacitor CS1 are electrically connected to each other asillustrated in FIG. 30 by conductive layers provided in first to seventhwiring tires.

Conductive layers 531_1 and 531_2 are formed in the first wiring tier.Conductive layers 532_1 to 532_4 are formed in the second wiring tier.Conductive layers 533_1 to 533_5 are formed in the third wiring tier.Conductive layers 534__1 and 534_2 are formed in the fourth wiring tier.Conductive layers 535_1 and 535_2 are formed in the fifth wiring tier.Conductive layers 536_1 to 536_7 are formed in the sixth wiring tier.Conductive layers 537_1 to 537_8 are formed in the seventh wiring tier.The conductive layers 537_1, 537_3, 537_4, 537_5, 537_6, 537_7, and537_8 have portions that serve as terminals SL, RWL, RBL, WWL, WBL, CN,and BN, respectively.

The transistor MW0 has a structure similar to that of the transistor 600illustrated in FIGS. 9A to 9D, and has an s-channel structure. Asemiconductor of the transistor MW0 consists of three oxidesemiconductor layers 540_1 to 540_3. The oxide semiconductor layers540_1 to 540_3 each contain an In—Ga—Zn oxide deposited by a sputteringmethod. The atomic ratios (In:Ga:Zn) of sputtering targets are 1:3:4 forthe oxide semiconductor layer 540_1, 1:1:1 for the oxide semiconductorlayer 540_2, and 1:3:2 for the oxide semiconductor layer 540_3.

The capacitor CS1 is an MIM capacitor and is formed of the conductivelayer 534_2, the oxide semiconductor layer 540_3, the insulating layer507, and the conductive layer 535_2. The conductive layer 534_2 includesthe node FN.

The conductive layers 534_1 and 534_2 are each formed of a stackincluding 10-nm-thick titanium nitride and 30-nm-thick tungsten. Theconductive layers 535_1 and 535_2 are each formed using 30-nm-thicktungsten. The conductive layer 535_2 is connected to a conductive layer(not illustrated) in the sixth wiring tier. The conductive layer 537_2is also connected to the conductive layer. With this wiring structure,the capacitor CS1 is electrically connected to a gate electrode of thetransistor MR1.

The insulating layer 507 is formed using 10-nm-thick silicon oxynitride.The insulating layers 505 and 508 are each aluminum oxide deposited by asputtering method to exhibit a blocking effect against oxygen, hydrogen,water, and the like. The thickness of the insulating layer 505 is 50 nmand the thickness of the insulating layer 508 is 50 nm.

The conductive layer 533_5 is provided so as to overlap with a channelof the transistor MW0, and the conductive layer 533_5 can serve as aback gate. In the prototyped chip, the insulating layers 504 and 505 aremade so thick that the conductive layer 533_5 docs not serve as a backgate electrode. The insulating layer 504 is formed using 600-nm-thicksilicon oxide, and the insulating layer 505 is formed using 300-nm-thicksilicon oxynitride. The conductive layer 533_5 is electrically connectedto the conductive layer 537_8 by conductive layers (not illustrated) inthe fifth and sixth wiring tiers.

≤≤Measurement of Off-State Current of Transistor MW0>>

An off-state current of the transistor MW0 was measured using themeasurement method shown in FIG. 2. Here, the off-state current of thetransistor MW0 at a temperature of 85° C. was measured.

<Step 1>

In the circuit MC10, a potential of the terminal RBL was changed whilethe transistors MW0 and MR2 were on to measure a current I_(RBL). Sincethe potential V_(FN) of the node FN was equal to the potential of theterminal RBL, data on title correspondence between the potential V_(FN)and the current I_(RBL) was acquired.

During the measurement, 3 V was applied to the terminal WWL, 1.1 V wasapplied to the terminal RBL, and 0 V (ground potential) was applied tothe terminals SL, CN, and BN. In addition, potentials were applied tothe terminal WBL in increments of 0.1 V from 0 V to 1 V.

<Steps 2 to 4: Retention Test of Circuit MC10>

During writing operation, 1.1 V was applied to the terminal WBL, 1.8 Vwas applied to the terminal RWL, 1.1 V was applied to the terminal RBL,and 0 V (ground potential) was applied to the terminals SL, CN, and BN.After that, 3 V was applied to the terminal WWL (Step 2). After 3 V wasapplied to the terminal WWL for a certain period, −1 V was applied tothe terminal WWL to make a data retention state (Step 3). Then, thecurrent I_(RBL) of the circuit MC10 in the data retention state wasmeasured (Step 4). In this manner, a graph showing a change in thecurrent I_(RBL) over data retention time (measuring time) was produced.

<Step 5: Results of Retention Test>

With the use of the data on the correspondence between the currentI_(RBL) and the potential V_(FN), which was acquired in Step 1, thecurrent I_(RBL) measured in Step 4 was converted into the potentialV_(FN). In this manner, a graph showing a change in the potential V_(FN)over the data retention time (measuring time) was produced. FIG. 32shows the graph. Note that here, the potential V_(FN) converted from themeasured current I_(RBL) is used as a measured value.

FIG. 32 shows the results of a retention test of the circuit MC10 at atemperature of 85° C. The lateral axis of FIG. 32 is a logarithmic axisthat represents the data retention time (measuring time). Thelongitudinal axis of FIG. 32 represents the potential V_(FN) of the nodeFN.

In data retention time of 612,000 seconds (17 hours), the potentialV_(FN) dropped from 1.1 V to 0.75 V. It is assumed here that the drop inthe potential V_(FN) is only caused by an off-state current I_(OFF) ofthe transistor MW0. Note that I_(OFF) can be expressed by a changeamount Qs of the capacitor CS1 over time, and I_(OFF)=dQ_(S1)/dt=C_(S1)×dV_(FN)/dt is satisfied, where C_(S1) represents the capacitance of thecapacitor CS1. The value of I_(OFF) calculated using this function is3.519 zA (3.519×10⁻²¹ A).

<Step 6: Determination of Parameters of Stretched Exponential FunctionDescribing V_(FN)>

To determine parameters of the stretched exponential functionrepresented by Formula (1), the stretched exponential functionrepresented by Formula (1) was fitted to the graph of the data retentiontest produced in Step 5. In addition, for comparison, an exponentialfunction was fitted to the graph of FIG. 32. FIG. 33 shows the results.A solid line indicates the measured data shown in FIG. 32, and twodotted lines are obtained by fitting the stretched exponential functionand the exponential function to the graph showing the measured data. Thedotted line denoted by “ExExp” in the graph is obtained using thestretched exponential function, and the dotted line denoted by “Exp” inthe graph is obtained using the exponential function. In FIG. 33, thelateral axis of FIG. 32 is converted into a linear axis. Parametersdetermined by fitting were as follows: τ=1×10⁷, α=1, and β=0.45 in thecase of the stretched exponential function, and τ=2.6×10⁷ and α=0.92 inthe case of the exponential function. This indicates that fitting to themeasured data was performed more accurately using the stretchedexponential function than using the exponential function.

<Step 7: Calculation of Stretched Exponential Function DescribingI_(OFF)>

As described in Embodiment 1, the off-state current low can becalculated by substituting the parameters of the stretched exponentialfunction determined by fitting of V_(FN) into Formula (4). FIG. 34 showsthe off-state current I_(OFF) calculated using the stretched exponentialfunction in FIG. 33. Parameters τ, α, and β are the same in FIG. 33 andFIG. 34. At data retention time of 612,000 seconds (17 hours), theoff-state current I_(OFF) is less than 1×10⁻²⁰ A, which is around 1 zA.

<<Examination of Retention Characteristics of Circuit MC10 UsingStretched Exponential Function>>

In the case where threshold voltage at the end of data retentionlifetime is 0.4 V in FIG. 33, that is, in the case where the minimumV_(FN) is 0.4 V, the data retention lifetime of the circuit MC10calculated using the stretched exponential function is approximately 100days.

FIG. 35 shows the dependence of V_(FN) described by the stretchedexponential function on the parameter β. The parameters τ and α in thestretched exponential functions in FIG. 35 are determined using themeasured value in FIG. 33.

In the circuit MC10, the extension of the data retention lifetimedepends on how much drop in V_(FN) can be prevented. FIG. 35 shows thatnot only relaxation time τ of the off-state current of the transistorMW0 but also β, which represents the variation in the relaxation time τ,are parameters important for data retention lifetime. Note that 0<β≤1 issatisfied from the properties of β. FIG. 35 shows that, β is preferablyas close to 1 as possible in order that the circuit MC10 can retainmultilevel digital data or analog data with reduced errors. For example,β is preferably greater than or equal to 0.8 and less than or equal to1, or greater than or equal to 0.9 and less than or equal to 1.

FIG. 34 shows that, in the case where the off-state current is the onlyfactor of the drop in V_(FN), the off-state current I_(OFF) of thetransistor MW0 becomes lower as the data retention time becomes longer.

Since t<<τ is satisfied, I_(OFF) can be represented by Formula (14),which is given by Formula (4).

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 16} \right\rbrack & \; \\{{I_{OFF}(t)} = {C_{S} \times \frac{\alpha \times \beta}{\tau^{\beta}} \times t^{\beta - 1}}} & (14)\end{matrix}$

Note that C_(S), τ, oαr, and β in Formula (14) are constants; as aresult, I_(OFF) can be represented by the power function y=A·x^(B) (Aand B are constants), FIG. 36 shows values of actually measured leakagecurrents of the OS transistor at a temperature of 125° C., and anapproximate straight line determined by the least-squares method. Theoff-state currents shown in FIG. 36 are normalized by the channel width.The channel length L and the channel width W of the OS transistor were0.8 μm and 10 cm, respectively.

To actually measure the off-state current of the OS transistor, theoff-state current needs to be high enough to be measured by ameasurement apparatus. An off-state current of a transistor whosechannel width is as long as several centimeters, which is very long, canbe actually measured. However, it is not realistic for a data retentioncircuit, such as the prototyped circuit MOO, to include such atransistor whose channel width is several centimeters to produce a highoff-state current.

According to the above, this example indicates that the method shown inFIG. 2, with which an off-state current is measured using the stretchedexponential function obtained from the measured values, is highlysuitable for measurement of an off-state current of a minute transistor.The channel length of a transistor subjected to the measurement ispreferably smaller than 70 nm, and may be smaller than 60 nm or smallerthan 50 nm. Note that the channel length is longer than or equal to 5nm, or longer than or equal to 10 nm.

The channel width of a transistor subjected to the measurement ispreferably smaller than 70 nm, and may be smaller than 60 nm or smallerthan 50 nm. Note that the channel width is longer than or equal to 5 nm,or longer than or equal to 10 nm.

This example also indicates that the measurement method shown in FIG. 2can be used to estimate an off-state current of a transistor severalmonths to several years ahead, which is longer than a period duringwhich retention characteristics are measured in Step 4. This means thatthe characteristic evaluation method of one embodiment of the presentinvention can be used to estimate long-term charge retentioncharacteristics. One embodiment of the present invention is veryeffective in reducing inspection time of a semiconductor device andimproving the reliability of the semiconductor device.

Example 2

In this example, temperature dependence of the potential V_(FN) of theretention node FN and the off-state current I_(OFF) of the transistorMW0 in the circuit MC10 is described. Measured values of the potentialV_(FN) at 85° C., 125° C., and 150° C. were obtained by a measurementmethod similar to that in Example 1. The stretched exponential functiondescribing the potential V_(FN) was calculated from the measured valuesof the potential V_(FN) at each temperature, and then, the off-statecurrent I_(OFF) was calculated. FIGS. 37A to 37C show the measuredpotentials V_(FN) at 85° C., 125° C., and 150° C. and the stretchedexponential functions. Note that the stretched exponential functions areindicated by dotted lines in FIGS. 37A to 37C; however, they are hardlyseen because they overlap with lines indicating the measured values.FIGS. 38A to 38C show the off-state currents I_(OFF) at 85° C., 125° C.and 150° C.

As shown in FIGS. 38A to 38C, the off-state current I_(OFF) of thetransistor MW0 at 85° C., 125° C., and 150° C. at measuring time of1×10⁵ s is less than 1×10⁻²⁰ A. Specifically, the off-state currentI_(OFF) at 85° C., 125° C., and 150° C. are 5.1×10⁻²¹ A, 7.4×10⁻²¹ A,and 8.7×10⁻²¹ A, respectively.

FIG. 39A shows a regression line obtained by plotting ΔV_(FN) at 85° C.,125° C., and 150° C. in FIGS. 37A to 37C. Note that ΔV_(FN) representsthe absolute value of the difference between V_(FN) in the initial state(the measuring time is 0 s) and V_(FN) at measuring time of 1×10⁵ s.

FIG. 39B shows a regression line obtained by plotting the off-statecurrents I_(OFF) at 85° C., 125° C., and 150° C. (the measuring time is1×10⁵ s) in FIGS. 38A to 38C. The off-state current I_(OFF) at atemperature lower than 85° C. can be estimated by extrapolation of theregression line in FIG. 39B. The off-state currents I_(OFF) at 60° C.and 27° C. at measuring time of 1×10⁵ s are 3.3×10⁻²¹ A and 5.6×10⁻²² A,respectively, for example.

This example indicates that the off-state current I_(OFF) of thetransistor MW0 described by the stretched exponential function isextremely low either at room temperature (27° C.) or at hightemperatures, and the off-state current I_(OFF) at measuring time of1×10⁵ s is less than 1×10⁻²⁰ A. This example also indicates that theoff-state current I_(OFF) at room temperature is less than 1×10⁻²¹ A.

This application is based on Japanese Patent Application serial no.2014-170756 filed with Japan Patent Office on Aug. 25, 2014 and JapanesePatent Application serial no. 2014-170757 filed with Japan Patent Officeon Aug. 25, 2014, the entire contents of which are hereby incorporatedby reference.

What is claimed is:
 1. A current measurement method for a transistorcomprising the steps of: writing charges to a first terminal of acapacitor through the transistor; making the first terminal of thecapacitor in a floating state by turning off the transistor; obtainingdata on a correspondence between a potential of the first terminal ofthe capacitor and measuring time; determining α, β, and τ in Formula(a1) by fitting Formula (a1) to the data, $\begin{matrix}{{V_{FN}(t)} = {\alpha \times e^{- {(\frac{t}{\tau})}^{\beta}}}} & ({a1})\end{matrix}$ wherein V_(FN) represents the potential of the firstterminal of the capacitor and t represents the measuring time; andcalculating an off-state current of the transistor by substituting thedetermined α, β, and τ into Formula (a2): $\begin{matrix}{{I_{OFF}(t)} = {C_{S} \times \frac{\alpha \times \beta}{\tau^{\beta}} \times t^{\beta - 1} \times e^{- {(\frac{t}{\tau})}^{\beta}}}} & ({a2})\end{matrix}$ wherein I_(OFF) represents the off-state current of thetransistor, C_(S) represents capacitance of the capacitor, and trepresents the measuring time.
 2. The current measurement methodaccording to claim 1, wherein a gate of the transistor is electricallyconnected to the first terminal of the capacitor, and wherein thepotential of the first terminal of the capacitor is measured bymeasuring a current flowing between a source and a drain of thetransistor.
 3. The current measurement method according to claim 1,wherein maximum measuring time is greater than or equal to 5×10² secondsand less than or equal to 1×10⁵ seconds.
 4. The current measurementmethod according to claim 1, wherein the transistor comprises an oxidesemiconductor in a channel.